AnsweredAssumed Answered

AXI_DMAC (how to configure adc_dma trigger interrupt on recieveing data block)

Question asked by Aban on Nov 1, 2017
Latest reply on Nov 2, 2017 by larsc

We have a picozed SDR SOM2 board with LINUX (from AD) running on it and we are able to stream through AD9361 radio using ad9361_iiostream.c and osc applications. 

 

How can I configure the adc_dma in the FPGA to trigger an interrupt when it receives data of 2k-2.5k bytes to send to the ARM cpu. Basically we don't want cpu to poll for incoming data. When the incoming frame is ready, trigger interrupt so cpu can read the frame data from DMA. 

 

The adc_dma is configured as FIFO interface (src) and MM interface(dest). How to specify TLAST or last of frame data here.  here are the input signals-

 // Input FIFO interface

  input                                    fifo_wr_clk,
  input                                    fifo_wr_en,
  input  [DMA_DATA_WIDTH_SRC-1:0]          fifo_wr_din,
  output                                   fifo_wr_overflow,
  input                                    fifo_wr_sync,
  output                                   fifo_wr_xfer_req,

 

The system has 2 nodes (boards) talking to each other. In the FPGA , we have a processing block which receive data block from ad9361 (RX). this is of length 1500-2500 bytes. How to transfer this via AXI_DMA , and it trigger interrupt to CPU.  Can you please point to some documentation or examples? This will be big help to configure DMA for high speed access from ARM-FPGA, we will appreciate it.

 

Using FIFO interface how can we notify DMA that we have sent complete frame and to trigger an interrupt (irq) when frame is transferred. larsc

Outcomes