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ADI AXI DMAC IP Core not meeting timing constraints

Question asked by pitch11 on Oct 31, 2017
Latest reply on Nov 1, 2017 by pitch11

Hello, first time posting so I am hoping this is done correctly.  I am currently working with the ADI AXI DMAC Ip core (High-Speed DMA Controller Peripheral [Analog Devices Wiki] , available from hdl/library/axi_dmac at master · analogdevicesinc/hdl · GitHub ) and I am currently having some issues meeting timing constraints within the Ip core.  I am not sure if it is something I am doing wrong in the use in my design and any help would be greatly appreciated!!

 

I am currently trying to implement the Ip core within Vivado 2016.2 for a Zedboard (Xilinx XC7Z020 chip).  Below is the block diagram.

 

 

ADI AXI DMAC Configuration:

 

The delay timing constraints are defined as following:

set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA0N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA0N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA0N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA0N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA0P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA0P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA0P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA0P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA10N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA10N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA10N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA10N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA10P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA10P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA10P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA10P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA12N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA12N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA12N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA12N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA12P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA12P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA12P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA12P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA14N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA14N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA14N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA14N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA14P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA14P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA14P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA14P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA2N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA2N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA2N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA2N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA2P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA2P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA2P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA2P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA4N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA4N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA4N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA4N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA4P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA4P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA4P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA4P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA6N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA6N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA6N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA6N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA6P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA6P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA6P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA6P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA8N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA8N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA8N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA8N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DA8P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DA8P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DA8P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DA8P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB0N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB0N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB0N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB0N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB0P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB0P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB0P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB0P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB10N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB10N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB10N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB10N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB10P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB10P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB10P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB10P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB12N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB12N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB12N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB12N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB12P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB12P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB12P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB12P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB14N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB14N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB14N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB14N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB14P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB14P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB14P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB14P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB2N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB2N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB2N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB2N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB2P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB2P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB2P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB2P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB4N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB4N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB4N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB4N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB4P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB4P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB4P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB4P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB6N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB6N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB6N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB6N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB6P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB6P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB6P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB6P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB8N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB8N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB8N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB8N]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -min -add_delay 1.020 [get_ports ADC_DB8P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -clock_fall -max -add_delay 1.430 [get_ports ADC_DB8P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -min -add_delay 1.020 [get_ports ADC_DB8P]
set_input_delay -clock [get_clocks ADC_CLKOUTP] -max -add_delay 1.430 [get_ports ADC_DB8P]

 

set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[0]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[0]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[1]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[1]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[2]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[2]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[3]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[3]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[4]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[4]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[5]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[5]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[6]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[6]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[7]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[7]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[8]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[8]}]
set_output_delay -clock [get_clocks clk_fpga_0] -min -add_delay -0.040 [get_ports {DELAY_D[9]}]
set_output_delay -clock [get_clocks clk_fpga_0] -max -add_delay 0.040 [get_ports {DELAY_D[9]}]

 

Here are some of the timing violations: (attached is the timing summary)

Intra-Clock Paths:

Inter-Clock Paths:

 

So the main question is what is causing these timing issues and how should I approach in resolving them.  I am fairly new to FPGA design and programming and any assistance would be greatly appreciated.  Thanks in advance.

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