In fractional mode, the setting of the phase interpolation parameter has an effect on the output frequency. This behaviour is not documented in the data sheet. The following example was set up on the development board:
Example: PLL2 with 50MHz input. register 8: 46562D93EE, register 9: 466650A0017, register 5: 00580000
This is an integer divider of 70, a fractional divider of 90364222, and an output divider of 88. S = 0 ( max phase interpolation)
The calculated frequency is 39,963,995.9997Hz. The measured frequency was identical with 100uHz resolution
Changing register 9 to: 46656A0017, with S=3 (no phase interpolation) gave an output frequency of:
39,963,995.9870 ( again with 100uHz resolution)
The frequency is different by 12.7mHz.
I usually use rational mode in my application, with S set to 3 (your recommendation). However if there is no solution in rational mode, I switch to fractional mode. I left S set to 3, and hence discovered the incorrect frequency, ie a frequency that does not agree with the fractional mode equation on page 26 of the data sheet.
Could you please clarify the effect of S on the frequency, and supply a new equation that includes S.
I would also be grateful if you could answer my question of the 28th Sept.
I have spent a great deal of development time on this device, and would appreciate a quick response to my questions.
Cosmo Little (RF Solutions)