I want to build a multi-frequency bio-impedance meter using ad9838 and ad40xx, the frequency range is 1kHz to 1MHz. ADC will start sampling exactly at the rising edge (toggling) of the MSB bit using the output of SIGN BIT OUT, and keep on sampling at a fixed interval until all 1024 samples have been collected. The MCLK is clocked by an output pin of a FPGA. The FPGA runs at 100MHz, and 10MHz is divided from 100MHz for MCLK.
The question is,
1, Can I source MCLK of AD9838 using the output of FPGA? Will the clock jitter affect the performance and may have worse SFDR, THD compared to the one use a CMOS oscillator?
2, The SIGN BIT OUT (MSB bit) is used as a trigge for an ADC (AD40xx) to start conversion, FPGA detect the rising_edge of MSB, and then generate a train of conversion pulses for ADC. Is SIGN BIT OUT synchronous with MCLK? i.e., SIGN BIT OUT is changed at the rising edge of MCLK. What is the setup time of SIGN BIT OUT after the rising_edge of MCLK?
3, For MCLK=10MHz, VOUT=1MHz, what is estimated SFDR? I could not find these specifications in the datasheet.