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AD9889B: No Video out and no TMDS out clocks

Question asked by sync on Nov 6, 2011
Latest reply on Nov 22, 2011 by DaveD

Hello,

 

I am a new user of the AD9889B device , the chip is being used on a Daughter board made by Microtronix. I am using this daughter card, on an FPGA Devkit board. My video path is as below..

 

From PC’s video card (HDMI port) -->  AD9880 on the D-card --> FPGA design --> AD9889B on the D-Card --> Monitor

 

Currently I am not able to obtain register value dump from the device, however I am able to read/write to individual registers.

 

Following are my observation..

-         HPD bit is correct.

-         Device is being initialized with following values..

    0x41, 0x10,     // Power Up device

    0x15, 0x00,     // Input Video RGB/YCbCr 4:4:4

    0x16, 0x00,     // Output Video RGB 4:4:4, Style 1, Clock on rising edge

    0x44, 0xf8,     // Enable S/PDIF reciever

    0x45, 0x00,     // Output format RGB

//    0x46, 0x00,   // SCAN info DEFAULT

    0x46, 0x08,     // SCAN info 16:9 output

    0x17, 0x02,     // Input aspect ratio 16:9 - bit (0) generated internal DE

    0x0A, 0x1c,     // MCLK ratio x128 fs as per RX chip settings - Enable S/PDIF enable Mclk for both I2s and Mclk

//    0x0b, 0x4e,   // MCLK falling edge

    0x0b, 0x0e,     // MCLK rising edge  

    0x0c, 0x00,     // I2S Audio disable

    0x98, 0x07,     // Reserved, required for correct operation -- changed to 0x07

    0x9C, 0x38,     // Reserved, required for correct operation

    0x9D, 0x61,     // Reserved, required for correct operation

    0x9F, 0x70,     // Reserved, required for correct operation

    0xA2, 0x87,     // Output drive strength, 0x87 needed for > 80MHz

    0xA3, 0x87,     // Output drive strength, 0x87 needed for > 80MHz

    0xBB, 0xFF,     // Reserved, required for correct operation

    0xAF, 0x06,     // Disable HDCP encryption - Select HDMI bit(1)

//    0xBA, 0x00,   // Capture phase adjustment 7:5 all others 0 (011 is positive edge, 111 is negative edge)

    0xBA, 0xe0,     // Capture phase adjustment 7:5 all others 0 (011 is positive edge, 111 is negative edge)

//    0xA1, 0x00,   // Enable HDMI TMDS channels (6:2) - to disable write 1's

    0xCF, 0x70      // Secondary register map address, change from 0x70 to resolve conflict with GPIO device (test)

 

-         I am providing 1920/1080 resolution from the Video Card, which the monitor, when connected directly identifies as 1080p.

-         A signal tap (embedded oscilloscope) in the FPGA is confirming that video going in and coming out is same, with few clocks latency. The design is currently in the  bypass mode. I also verified DE to be 1920 cycles long.

-         I have confirmed that clock, Syncs/DE and Data (on some lines only) are reaching the AD9889B, from the FPGA.

-         When I scoped TMDS clk+, I found only some +ve DC offset there and clk- was simply at GND level. Even with AC coupling I see no clocks on these lines, with scope at about 500 mV.

-         I noticed that reg 0x3E was reading back 0x40, which implies that AD9889B is detecting the format as 1080i.

 

I am running short on ideas to further debug this chip and would appreciate any help. Please advice which registers I must further check to ensure that the Device is correctly configured and I can get TMDS clocks.

 

Regards,

Jaspal

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