AnsweredAssumed Answered

Issue with generated library blocks

Question asked by F.Shahin on Oct 26, 2017
Latest reply on Oct 30, 2017 by travisfcollins

Note: I'm posting this issue here because my first post was moved to this sub-forum. I apologize for any inconvenience.

 

I've been stuck with a problem for few days now. I've made some modification to the "Targeting HDL Optimized QPSK Transmitter Using Analog Devices AD9361/AD9364" example in MATLAB to modulate the signal using 4-QAM instead of QPSK. When running the simulation of the system, the constellation at the receiver shows correct results. I went through all of the "HDL Workflow Advisor" steps successfully. However, when I construct the transmitter system using the blocks from the library created during the "HDL Workflow Advisor", I don't get any correct results. The simulation is run in "External" mode. The next two screenshots show the transmitter circuit and the constellation of the received signal. I should note that the constellation "After Timing" keeps jumping between the 4 locations where a correct 4-QAM constellation should be.


However, when I use the exact same blocks for transmission with the "ZedBoard and FMCOMMS2/3/4 Transmitter" block which comes with the communication systems toolbox, the transmitter works without any problem. Of course, I've unchecked "Bypass user logic" option for the transmitter block. The next two screenshots show the transmitter circuit and the constellation of the received signal.

 

For me, it's important for the first system to work because in the near future I will need to send and/or receive some control signals to/from the FPGA. Is there any explanation why the first system doesn't work? Do I need to set some options before running the simulation?

Outcomes