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ADV7341 CVBS 720x576 @50Hz progressive

Question asked by DJango991 on Oct 24, 2017
Latest reply on Oct 25, 2017 by Anthony_Purcell


I tried to obtain the 720x576 @50Hz progressive resolution over the DAC 4, connected to a CVBS connector, using the configuration reported on Table 82 shown on the datasheet and enabling the SD noninterlaced mode (bit 1 in the SD Mode Register 7). The input data to the chip are generated using an FPGA. However the video generated from the chip is corrupted. Instead, the SD Color Bar (enabled with the bit 6 in the SD Mode Register 4) is reproduced correctly.


What is the matter?


Previously, I configured the chip to receive the resolution of 1280x720 @50Hz progressive and the video generated over DAC 1 - DAC 2 - DAC 3, connected to a VGA connector, is correct.