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AD9467 Project on KC705: how do I know when the project completes the project properly?

Question asked by clanzl on Oct 23, 2017
Latest reply on Nov 8, 2017 by CsomI

I have an AD9467_FMC 250Msps evaluation board and a Xylinx KC705 evaluation platform, and I have been working for 3 weeks to get the AD9467 evaluation board up and running on the KC705 in a CentOS 7.3 Linux environment running in a VMware virtual machine under VMware Workstation 12 Pro on a Lenovo ThinkPad T430s (16GB RAM, 500GB SSD).  CentOS 7.3 has a dedicated processor, 2GB of dedicated RAM and 100GB of dedicated storage.   Following the wiki https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467, I have successfully loaded the project files (2016.2, as best I can tell; there are 2017 files as well, but the wiki appears to indicate that 2016.2 is the most current release).  The AD9467 project appears to have terminated, but it is not clear to me that the termination was successful.  I should stress that I am an RF engineer, so I am not at all familiar with FPGA work, I'm just trying to get the vanilla AD9467 evaluation board up and running on the KC705.  I have attached the Vivado log file (rather large).  How do I know when the AD9467 project has terminated successfully and generated the appropriate bitstream to load into the KC705?  If the project has not terminated properly, what should I do to fix any errors?  Thanks, Colin 

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