For a while now, I've been trying to solve the last few little hiccups getting 5 ADF4350 synthesizers to sweep together coherently. Without getting into all the messy details, we need to generate two distinct frequencies, an intermod frequency, and some down conversion frequencies. At the end of the conversion process, we want to measure a residual phase, so we are concerned with phase coherence, and need to use phase resync. Phase resync requires that any output division also appear in the feedback loop. Additionally, Register 0 of each synthesizer needs to latch on the same reference clock cycle with almost no jitter with respect to the other synthesizers.
By this time I am fairly certain the correct programming words are being sent and that I have dealt with any timing or glitch issues I may have previously had. Likewise, I am fairly confident we have a good layout with adequate attention to RF considerations, power, and signal bypassing.
It goes without saying that the loop dynamics of each synthesizer must also be right, and I believe they are, because I get a very pure signal with no humps or other funny things in the noise floor that would be indicative of poor loop stability. Still, perhaps once every 1,000 phase locks, I still see a lock failure I cannot explain. Sometimes the signal completely vanishes; other times it is just way, way off. These lock failures make me wonder if the ADF4350 may have incorrectly chosen which VCO to use.
The datasheet is vague about the inner workings of the band select logic other than to say the VCO core is disconnected from the charge pump and connected to an internal reference. Furthermore, we know that it takes 8 PFD cycles (at 1MHz Fpfd) to complete a band selection. I suspect that during this process, the phase-frequency detector must be getting monitored as the band select logic switches different VCOs in and out. Some of these VCOs will be below the reference frequency; the rest above it. The appropriate VCO should be the one which is nearest in frequency to the reference, and would correspond to where the VCOs crossed from being on one side of the PFD to the other. Using a bisection algorithm, one might divide the VCOs into upper and lower 16, then upper and lower 8, then 4, and so on, until the correct VCO was determined.
Assuming I'm on the right track, I wonder if there might be some situations where the PFD could sometimes indicate incorrectly for a PFD cycle or so. It seems unlikely that there is anything but random phasing between individual VCOs, so it's possible to imagine a situation where, for one (perhaps two?) cycle, the PFD could temporarily indicate incorrectly, perhaps leading to a very bad choice of VCO, and causing the indications I have seen.
So, at last we come to my questions. Is this a possibility? Will setting the BS divide clock to a larger value than the minimum recommended one do anything to solve this potential hazard? Is there any more light you might be able to shed on this subject, as well as what else might be happening?
What do you guys think?