AnsweredAssumed Answered

can not enable data cache (Bank A).

Question asked by qian on Nov 5, 2011
Latest reply on Nov 8, 2011 by PrasanthR

hi
  all

my bf561-0.5 development board  use 128MB SDRAM(64MB x 2)。

 

Project configuration is:

Use external memory (SDRAM)  128 MB
system heap    L3  13MB
system stack   L3  1MB

 

SDRAM-xml:
<custom-register-reset-definitions>
     <register name="EBIU_SDRRC" reset-value="0x0390" core="Common" />
     <register name="EBIU_SDBCTL" reset-value="0x27" core="Common" />
     <register name="EBIU_SDGCTL" reset-value="0x0091998F" core="Common" />
</custom-register-reset-definitions>

 

 

When I enable data cache (Bank A),program will not load。
Then disconnect the IC and the dsp on a link .


Test procedures in Annex.

thank you.

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