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ADV7842: Difficulty configuring for component input

Question asked by Box on Oct 20, 2017
Latest reply on Nov 16, 2017 by Box

We are using the ADV7842 in our product and I am currently attempting to configure the device to capture component video. HDMI input works fine but I'm having a difficult time getting the component processor to lock on to the incoming component signal. The analog front end I believe is set up right; I set PRIM_MODE to 0x01 and VID_STD to 0x13 (and other values e.g. vertical frequency). Both CH1_STDI_DVALID and CH1_SSPD_DVALID read 1 so it appears that the STDI block is getting (near) valid results:

 

CH1_BL = 5088 (expected 5091)
CH1_LCF = 749 (expected 750)
CH1_LCVS = 5 (expected 4 to 5)
FCL = 1866 (expected 1868)

but the CP never seems to indicate a lock. What other configuration settings am I omitting? Can the inaccuracies above cause issues as well?


I have attached i2c register dumps of the AFE, CP, and IO spaces; I'll provide additional detail as needed.

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