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Whether the device 125MHZ complete DDS synthesizer AD9850 can be used for generating clock input for FPGA for doing communication system demodulation

Question asked by Kalkikrishna on Oct 20, 2017
Latest reply on Oct 23, 2017 by Kalkikrishna

Whether the device 125MHZ complete DDS synthesizer AD9850 can be used for generating clock input for FPGA for doing communication system demodulation(BPSK,QPSK and spread spectrum systems).The requirement is 1ppm clock source for the application. We can give 1ppm ref clock to the DDS. Whether the genrated clock from DDS will be 1 ppm and can be used for communication system receiver implemented in FPGA.Thank you

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