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The axi_ad9361 IP do not support for TDD mode?

Question asked by xiecongshuaige on Oct 20, 2017
Latest reply on Oct 25, 2017 by rejeesh


   I found that P0 and P1 are one-way interface in axi_ad9361 IP. One for input another for output like the define below.

   It's only support for FDD mode.But when I look at the reference manual I found that if we want to use TDD mode,P0 and P1 should be defined as bidirectional interface like below.P0 and P1 should be defined as inout port.

    So,the axi_ad9361 IP don't support for TDD mode.I want know what shuold I do(what should I change in hdl or something else) if we want to use the TDD mode?

   Thanks a lot and sorry for my poor English.