I am designing a simple 500MHz output PLL by 25MHz Oscillator as the reference clock for REF pin of HMC3716, HMC3716, differential-to-single ended amplifier as the loop filter, 500MHz output VCO and HMC394 (setting N=20) divider, whose output is for the NREFpin of HMC3716 in PLL loop.
For HMC394, the duty cycle is inversely proportional to N. In my case, N=20, the duty cycle is 5%. Since HMC394's output clock for HMC3716's NREF is 25MHz, the pulse width is only 2ns.
I am curious if HMC3716 can detect this 25MHz signal by "5% duty cycle" (2ns pulse width) at its NREF pin. In HMC3716, it can compares the rising edge of the two input signals (REF / NREF) so it is no problem to compare the non-50% duty cycle input signals. But is there any concern of the setup time and hold time when doing the comparison?