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Synchronizing the AD9671

Question asked by BiK on Oct 19, 2017
Latest reply on Nov 6, 2017 by BiK

We have problems to synchronize the AD9671. It seems that the FPGA doesn't recognize the K28.5 characters. We clock the AD9671 with 100Mhz, so we should be in Mode 4. The RF decimator must be turned on, so the data rate is 50Mhz. The 8 ADCs of the device use 4 lanes to transfer their results. With 8B/10B we have 2Gbps on one lane. To avoid errors we used the SPI Write Start-Up Sequence Example (on page 46/47 of the data sheet) with some little changes. Could you please so kind to check our settings? I marked the differences to the Start-Up Sequence example in red color.

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