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AD9364 RX channal configration

Question asked by huangyu on Oct 19, 2017
Latest reply on Oct 26, 2017 by huangyu


   i have two AD9364 on my board,one is used as TX,the other used as RX,i configure the both chips in FDD mode,with rx LO 1090MHz,TX LO 1090MHz,BBPLL 983.04MHz,HB1~HB3 interpolation by 2 (both tx and rx chain ),fir filter bypass,and the baseband sine signal is generated by FPGA,with the frequency is 200Khz,now the tx signal is 1.0902GHz,-2.7dbm,but the odd hatmonic is also existed,is this correct?,when use FPGA capture the rx data ,which receive the i&q signal with the frequency 200KHz,is this right? the other quesion ,when i change the TX  LO RX LO 、BBPLL frequency、data_clk ( no other register is changed),tx signal is always right,but rx signal is wrong,which worries me so much,the question is,if there  are more registers i shuld config?and what registers?,and what the relationship between BBPLL、TX  LO、RX LO、(ADCDAC),or  i can configure them by my own ideas,thanks!