I am working with AD-FMCDAQ2-EBZ on KC705 board. I first implemented a HDL design with microblaze in Vivado. In the design, I have a JESD204B core and a JESD204B PHY core.
The JESD204B is used as a transmitter of AD9144. The JESD204B core is configured as 2 lanes/Link, 2 Octets per frame, 32 frames per multiframe, it data input port tx_tdata[63:0] is connected to a constant value tx_tdata=64'h00000A0000000A00, Its AXI4-Lite port is connected microblaze.
The JESD204B PHY core is configured as 2 lanes/link, link rate 10Gbps, reference clock 500MHz, PLL type QPLL, and its AXI4-Lite interface is disabled.
After generated bitstream from this design, I launched to SDK. I downloaded the latest driver files from Github (2017.R1). The files I used including fmcdaq2.c, platform_driver.c, ad9144.c, ad9523.c, ad9680.c and their corresponding headers. I did not use any AD/DA core drivers because I do not have those IPs in my design, I also did not choose JESD drivers because I already set them in the design and I do not want to change them.
In fmcdaq2.c, I deleted all the codes related to AD/DA core drivers and JESD204 drivers, to make the it executable. After run this software, I detected some monitor clock signal on FPGA board (I connected the TXCLKOUT of JESD204B PHY core to a SMA output port on FPGA), so that means the ad9523 setup part is successful. But I did not see any output from AD9144 output 1. since tx_tdata=64'h00000A0000000A00, I should see a 500MHz square signal.
The PLL of AD9144 is locked because I did not receive the "PLL Not locked" message. But I received the following message:
ad9144_status : CGS NOT received (3)!.
ad9144_status : ILAS NOT received (0)!.
ad9144_status : framer OUT OF SYNC (0)!.
ad9144_status : check-sum MISMATCH (0)!.
Any suggestions to debug this issue? The corresponding codes have attached.