Questions: Would using the "synchronized data sampling" feature of the ADXL372, i.e. providing a clock signal to INT2 pin successfully resolves the FIFO misalignment issue that occurs due to internal clocks clashing?
Answer: It will not solve the problem. The only way to avoid the issue is to stop the ADC from sampling while you read the FIFO. That is what is described on the DS workaround. Please have a look at ADXL372 FIFO workaround using external clock (INT1) for the details.