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ADT7310 Dout High Impedance

Category: Hardware
Product Number: ADT7310
Software Version: N/A

Hello,

I’m using the ADT7310 and am wanting to put a weak pull up or pull down on the Dout line to ensure the line is held at a valid cmos input range when cs is de-asserted. I understand the chip takes the line to high z when cs is de-asserted, but is there a voltage the output is weakly pulled to such that when connected to a standard cmos input, the line will be at a known and valid voltage level for the input. 

thank you!

  • Hi  ,

    The output of the DOUT/MISO pin of the ADT7310 is left floating when not used (No, it is not weakly pulled to any voltage). 

    If your controller has no internal weak pull-ups, then you can attach a pull-up resistor to keep the CMOS from unnecessary current consumption. Just make sure however, that you find the right balance between the power consumption and good signal integrity(make sure that logic high can still be read by the input), when installing the pull-up resistor.

    Regards,
    Karlo

  • Hi Karlo,

    Thank you very much for the response. The reason I ask is I currently have a 1Meg pull down on the line and it causes the line to idle at 1V. Removing the 1Meg, the line idles at 3.3V (Vcc powering the IC). Replacing the 1Meg with a 100k pull down, the line idles around 120mV. This tells me there’s approximately 2.5Meg of impedance to the rail when Dout is idle. Is this just the net impedance to the rail of the output stage? If so, do you know what the typical value is? I would have thought a 1Meg pull-down sufficient to pull down the output when idle, while also not impacting signal integrity with additional loading. 
    Have you all done characterization on a maximum pull down or pull up that will appropriately bias the Dout line during idle times?

    Thank you!

  • Hi  ,

    Would you please enlighten me on your setup so that I can assist you properly? What microcontroller are you using to control the ADT7310? Are you using an eval board, or a custom PCB? I would also like to ask how you're measuring the voltage in your last reply, is the ADT7310 connected to your microcontroller?

    Regarding the characterization, I don't think it has been done for the part. Could you share what exactly is your application, and why you need a pull-down resistor for the Dout pin of the SPI?

    Thank you and regards,
    Karlo

  • Hi Karlo,

    I’m using a Microsemi Igloo FPGA to control the ADT, and it is currently running on a custom PCB. 
    Currently the setup is the Dout line from the ADT is connected to a CMOS TTL I/O on the FPGA. The only other thing on the line is the 1Meg pull-down to ground that I previously mentioned. The ADT and FPGA I/O bank is powered from the same 3.3V rail. 

    I’m using a scope to take the voltage measurement, and the scope has a 10Meg termination in it, so when the scope prove is connected to the Dout line there’s 10Meg to ground in parallel with the on board pull-down. I’ve taken the measurement with the FPGA connected and with it disconnected. There’s no idle voltage difference in those two cases, but there is an idle voltage difference when the 1Meg is removed and when the 1Meg is replaced with a 100k (see response above). Just to note, in addition to the idle voltage, I can see the SPI transaction occur, and the chip drives rail to rail during the transaction. It’s only when it idles the Dout line that we have this middle voltage occur. 
    I want to use a pull down so the line is in a known state when the ADT takes the line high impedance. For this FPGA, it’s I/Os need to be kept within valid CMOS input levels, so floating lines need to be put into an intentional state. The pull-down was an attempt to keep the line low when the ADT makes it high impedance. 
    Do you think a pull up or pull down would better solve this issue, and what is the largest value you could recommend using? Also, do you think this is repeatable, ie any ADT7310 will tend to pull up the output, or do you think it’s variable from chip to chip? 
    Thank you for your help!

  • Hi  ,

     If there is indeed an internal weak pull-up, then I'd suggest just using a pull-up too, as using a pull-down would provide a path from supply to ground, leading to unnecessary power consumption. If you decide to use a pull-down resistor, the largest value of resistor would then depend on the low state the FPGA(CMOS) input can recognize. Please refer to the datasheet of the Igloo to determine the maximum voltage level for a logic low.

    For your last question, I would have to check, but it is most probably repeatable, as you're seeing a consistent probable pull-up of 2.5Meg when changing your pull-down resistors. 

    Thanks.

    Best Regards,
    Karlo

  • Hi Karlo,

    Thank you for your reply. The pill-up is the way we’ll go. I guess I have just a couple more questions:
    Is there any way to confirm the approximate value of the pull-up impedance internal to the ADT? I know that I’ve characterized one IC to be approximately 2.5Meg, but is there any way for AD to estimate based on testing or output stage design what the impedance should be?

    Is there any way to confirm if this approximate impedance will be consistent from IC to IC?

    Thank you very much for your help!

  • Hi  ,

     I don't think there's a way to exactly determine this impedance, as I have tried testing it myself, varying the pull-down resistor. The said calculated impedance changes (From 3Meg down to 1.8Meg) with varying pull-down resistors. 

    I think the way to approach your concern is to use a relatively-low pull-up or pull-down resistor to make sure that the DOUT line is always at a valid CMOS input level. Again, this is dependent on the specification of your FPGA input. The most common approach is to use a resistance in the tens of kiloohms range (General rule of thumb is to use 10kohm resistors).

    I hope I was able to help.

    Regards,
    Karlo

  • Hi Karlo,

    Thank you for the reply. I completely agree with you on the relatively low resistor selection. My last question on this thread before we close it is, will the output stage tend towards the rail or ground? It seems like in your testing and what we've seen, the output tends towards the rail, but is that expected based on the output stage design of the IC?

    Thank you again!

    Tyler

  • Hi  ,

    The output is again in High Impedance state when the bus is idle, it should be floating and not biased towards any rail. Again, using a relatively low resistor would help you decide and ignore the bias of Dout (towards any rail) when the bus is idle. 

    I hope this helps. 

    Regards,
    Karlo