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LTC2991 Data Valid Clearing Incorrectly

Category: Hardware
Product Number: LTC2991

When reading a certain LSB inputs, we are seeing the data valid bit clearing for other inputs.

For example, we have set 0x08 to single shot and trigger a read of all the inputs by writing 0xff to register 0x01. 
Before reading any of the inputs we read register 0x00 (status low) which outputs 0xFF indicating that all the registers contain new data. 
Afterwards we read register 0x0B (LSB for V1) which outputs its voltage LSB value.
However, when we read the status register again (0x00), it outputs 0xfc (11111100) which indicates that both v1 and v2 have old data.

During testing this issue happens with all LSB affecting its preceding input (ie. v2 LSB clears v3 data_valid flag).

We tried setting all inputs as single ended but still see the same result. Testing the I2C signals on an oscilloscope confirms that the read/write packets as the same as read through console. Our I2C CLK freq is less than 400Khz. 

Is there some other setting we are missing? This happens across multiple boards.

[edited by: LouisWeride at 10:15 PM (GMT -4) on 27 Oct 2022]
  • Hi Louis,

    I need to check the behavior of the chip for your reported problem.  I assume you have read the paragraph on pg 16 that covers the Status Register.

    How quickly are you reading the ADC values?  Are you suspecting the ADC values are stale?


  • We are manually reading the ADC values through a MCU console attached to the i2c device during this test, so relatively slow. As fast as we are able to type in the i2c commands into console. 

    The ADC are in single shot so we are expecting the data valid flag for an input only to be cleared once we read from the input. We are confused why reading values out of one input is changing the data valid bit of another input.

    Issue is later if we try to read all the inputs consecutively quickly, it will say sequential inputs are "old value" since the preceding value reading cleared their data valid even though the input is not "old". (example: reading V1 also clears V2 "data valid", so when we read v2 after reading v1 we see v2's data valid flag is cleared even though it shouldn't be)   

  • Hi Louis, I confirmed your finding but not sure why the adjacent data valid bit is cleared. However after using a script, I found in all tested cases that bit15 of the MSB does indeed get set, signifying that the data is valid.  I hope this helps.


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  •    Thanks for the test! Also tried it out and see the same thing. If I don't use reg 0 (data valid), the input's MSB bit15 seems to behave as expected (only clear when value read)
    However, if I try and read the the data_valid reg0 between every input read, then the bit15 gets cleared incorrectly. 

    This does mean I can only tell if an input is valid/updated is by reading its MSB and using bit15 instead of just reading reg0 to check all of the inputs correct? 

  • It seems that reading only the MSB (regs 0x0A, 0C, 0E, 10) followed by reading status 0x00 results in the correct data valid bits in the status register.  Trigger a conversion, read status, read V1 msb, read status, read V2 msb, read status, read V3 msb, read status, read V4 msb, read status.  The status correctly reads back 0xFF, 0xFE, 0xFC, 0xF8, 0xF0.


  • Yeah we see the same. Reading the LSB affects the next input if using the reg 0x00 status valid but not the MSB bit15 valid.

    Though in normal cases we probably need to read the MSB and LSB of a single input before moving to the next. Not read the MSB of all the inputs and then the LSB.
    So seems like there is a bug with the data_valid reg0x00. We'll stick to just using the MSB bit15 then.