ADT7320 setup

Okay, it looks like my setup is catching an extra bit...if I look at the results with a logic analyzer SPI, the "extra" 1 is from the first 8 bits of 24 bits, so the second byte is returning the proper register contents. I will try changing the configuration register and then reading temperature.

Todd Anderson 

Hi, Todd.

If you could share screenshots of the SPI interface it would be nice. I wouldn't recommend reading the temp just yet if you're not getting consistent correct readings as per the quick guide on the datasheet. Slow down your SCLK too, timing specs on page 4 show both high and low pulse widths require minimum of 100ns. 

Regards,

Karen

Karen:

Thanks for pointing that out. I reduced my SCLK to 5 MHz, and all is well.

Regards,

Todd Anderson

Karen:

Thanks for pointing that out. I reduced my SCLK to 5 MHz, and all is well.

Regards,

Todd Anderson