What is Latch-up and how are these parts immune to it?
- Latch-up is an undesirable, high current, state that can significantly reduce the lifetime of a part or cause permanent damage and failure. Junction-isolated CMOS switches exhibit a silicon-controlled rectifier (SCR) circuit when the parasitic junction diodes become forward biased. With trench isolation technology, each N-well and P-well is physically separated by an insulating oxide layer and the parasitic diode is removed. This results in a switch that is immune to latch-up under all conditions.
Are Latch-up immune parts over-voltage fault protected?
- No. The latch-up immune family is more robust to transient voltage spikes on signal lines than typical CMOS devices but they cannot be relied upon to protect downstream circuitry.
What if I need to protect my device or downstream circuits against over-voltages?
- This application note provides a lot of detail into the over voltage protection of CMOS switches and multiplexers and is generally applicable: link
What is the ESD rating of these devices and what is the benefit of the rating?
- These devices have been rated to 8kV Human Body Model. This helps reduce requirements for system level protection and increases robustness to handling concerns during manufacturing.
What is the minimum voltage that can be used with these parts?
- VDD = 9V is the minimum supply voltage to guarantee the digital input voltages are 3V compatible across all voltage and temperature ranges. The supply voltage can be lowered to VDD = 5V if the digital inputs are driven to VDD too.
What is the recommended supply sequence?
- The Golden sequence for power up is; Ground, VDD, VSS, Digital Inputs. The trench isolation and lack of logic supply pin (VL) means that it is not possible to cause latch-up in these parts by an improper supply sequence. However, it is still good practice to follow the Golden sequence whenever possible.
How should I manage unused or Not Connected pins?
- Pins described as Not Connected in the data sheet are not internally connected. It is not necessary to tie these pins to any voltage. Digital pins always require a known voltage as to leave them floating can cause internal digital logic to be in an indeterminate state and cause invalid operation of the part. Unused digital logic pins should be tied to GND or digital high.
What are suitable applications for these parts?
- This family of parts has been optimized to provide a low resistance channel between the Source and Drain pins, with minimal difference between the maximum and minimum resistance value. They are particularly suitable to applications where low channel resistance, minimal distortion or high dynamic range is required, such as: High voltage signal routing, battery stack monitoring, relay replacement or other analog front-end circuits.
I like the robustness of these parts to PSS issues and the good ESD performance but my application needs lower capacitance and good leakage performance.
- The ADG52xx family has been built using the same trench isolation technology and has been optimized for low leakage, low capacitance, and low charge injection.
Can I leave the exposed pad floating?
- The exposed pad is connected to the substrate which in this case is the most negative voltage, Vss. The exposed pad should be connected to Vss to enable more efficient heat transfer and increase reliability. There is no impact on switch performance if exposed pad is left unconnected but heat dissipation will not be optimized. Connecting the exposed pad to anything other than Vss potential may cause high current flow, affect the switch performance, and the long-term reliability of the part.
These parts are good, but I need lower on resistance at ±15V. Do you have any compatible parts?
- Please consider the ADG14xx family of parts, which are pin-to-pin compatible with the ADG54xx family: The ADG1419 is specified as a 2Ω switch at ±15V supply and is pin-to-pin compatible with the ADG5419
Do you specify switch Off Resistance?
- No, but the Off Resistance across a switch can be calculated using the off leakage specifications given in the datasheet. For example: Using the +12V data for off leakage at 85°C of the ADG5401; IOFF = 2nA (MAX) and this is measured with +1V to +10V across the switch. Therefore: V∆ = 9V, and the minimum ROFF is 4.5GΩ at 85degC.
