To help explain changes in Idd when using logic control line drive voltages different than those used in the Idd section of a datasheet consider the picture below. It shows the logic control input for a CMOS single supply switch that uses an inverter/buffer which is biased from Vdd to Ground. In this example an increase in Idd current can be seen if a logic high drive voltage less than Vdd is used. This occurs because when using a gate drive voltage less than Vdd the PMOS off switch (upper switch in the diagram) will not be fully “off”, so you start to draw some current from Vdd to Ground. The lower the drive voltage is from Vdd the greater the leakage current will be, it typically reaches a maximum at the minimum on-threshold level of the switch (example 2V). This is common in CMOS devices and should be considered when using logic driven CMOS components.
In summary when looking at the Idd section of a switch datasheet note the voltage drive levels used. If a drive voltage less than this is used (e.g. 3.3V logic high with Vdd=12V) then Idd can be affected and may need to be considered in a design. The magnitude of change in Idd will depend on the switch family and voltages used. See figure Figure 14 in the ADG1412 datasheet for an example of this change in Idd for a high voltage part using different drive voltages. The closer the logic control line high drive voltage is to Vdd the less Idd leakage there will be. For lower voltage switches (e.g. ADG8xx and ADG7xx families) the Idd change will be less compared to higher voltage parts since Vdd is lower.
An important note. Notice on a lot of CMOS parts the logic control line drive voltage references not Vdd but a Vl pin voltage. Where there is a Vl pin on a part you can set this to the same voltage as your logic input high value, and thus will avoid the situation described above.