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  • +Documents
  • 1. Thermal Resistance Junction to Board (Theta JB): 2. Thermal Resistance Junction to Case (Theta JC):
  • 3.3V VL logic supply for ADG2128
  • AD8152 EVB
  • AD8152: Connection of DC inputs
  • AD8152: used as a DVI switch
  • AD8152_switch HDMI signals
  • AD8156: Can I drive AD8156 from LVDS and LVCMOS sources?
  • AD8156: multiplexer and OOB feature
  • AD8159: Layout
  • ADG1204: Connecting the exposed paddle to Vss
  • ADG1204: Optimal impedance level
  • ADG1204: What is the optimal impedance level for source and load to apply?
  • ADG1219: Spice modell to simulate the charge injection?
  • ADG1219: Supply voltage
  • ADG1236: Charge injection
  • ADG1409: ADG1409: Process technology / MTBF
  • ADG1434: IBIS model
  • ADG1436_leakage current
  • ADG1604 DC "Off resistance"
  • ADG1612: Minimum supply voltage
  • ADG2128 Output stage ( Hi, Lo, Hi Z) of the I/O when the switch is off
  • ADG3123: Maximum Output Signal Swing
  • ADG3247:  Hotswapping
  • ADG3248: number of logic gates transistors used
  • ADG324x: Level Translation of ADG324x Bus Switches
  • ADG324x: Maximum Pass Voltage of the ADG324x Bus Switches
  • ADG3300/01/04: Input Driving and Output Load Requirements
  • ADG3300: Can I work with VCCA = VCCY?
  • ADG3304: Is this device compatible with I2C?
  • ADG3304: used as I2C level shifter
  • ADG3304_power up sequence
  • ADG3304_protection method
  • ADG3308 and indeterminate i/p o/p state's interface  query
  • ADG3308 bidirectional, setting the direction
  • ADG3308: Design queries
  • ADG3308: Input Driving and Output Load Requirements
  • ADG330x unused inputs
  • ADG330x: devices is heating up - what is the reason
  • ADG330x: Level Translator for I2C Applications
  • ADG330x: Source and Sink Currents
  • ADG333A switching frequency / bandwidth information?
  • ADG333A_Status_WhenInputFloat
  • ADG406: Unpowered usage
  • ADG409: Minimum power supply
  • ADG411: is ist possible to worf with a 3V Logic Level?
  • ADG411: logic threshold voltage over digital supply.
  • ADG412: Lower voltage supplies than specified
  • ADG419: supply voltage
  • ADG426_leakage data at 60C
  • ADG428:  Descrepancy between maximum operating temperature in selection tool and web page order guide
  • ADG438F: Bidirectional or unidirectional
  • ADG442: low logic level clamped to about -1V.
  • ADG451: Latch up
  • ADG451BR: Spectral Noise Density
  • ADG452: GND connections
  • ADG452: VL = 15V possible not not recommendable
  • ADG453: Perfomance from +/- 15 V power supply
  • ADG453: Power Up Sequence
  • ADG467: Fault free input range
  • ADG506: Overvoltage on the input
  • ADG506: Pin connection
  • ADG508 ADG509_digital control voltage range
  • ADG508A: Enquiry for product specification
  • ADG508AKN: Robustness
  • ADG508_thetaJC and maximumTJ
  • ADG5208: THD specifications missing at the ADG520x family
  • ADG5404, ADG1406, ADG442: case temperature:
  • ADG5436_unbalance power supply
  • ADG54xx Latch-up immune switches and multiplexers FAQ
  • ADG601: Digital input from a FET
  • ADG621_spec for 3.3v supply
  • ADG623: ESD Lavel for the AGD623
  • ADG659: Supply voltage
  • ADG701: Noise
  • ADG706: +/- 5V supplies
  • ADG706: Grounding
  • ADG706: Working as a demultiplexer
  • ADG708: Multiplexing 3V3 logic signals
  • ADG709: Life time
  • ADG712: overvoltage protection
  • ADG715 Operation with VDD=VSS=0V
  • ADG728: Input and output current for safe operation
  • ADG732 LFCSP exposed Pad
  • ADG733: Noise specification
  • ADG734 in audio application
  • ADG734: Usage without supplies
  • ADG788: ESD rating
  • ADG788: How much ESD can the ADG788 take?
  • ADG801_parallel multiple switch to reduce Ron
  • ADG804: Maximum voltage
  • ADG819BRM's branding is "SBC" although in the datasheet states "SNB".
  • ADG819_switching current
  • ADG884 Overvoltage
  • ADG884: Bandwidth simulation
  • ADG901: Max current
  • ADG936_About the insertion loss between DC to 50MHz
  • ADGS1412 FAQ
  • ADN4600 Design Support Files
  • ADN4604 Design Support Files
  • ADN4605 Design Support Files
  • ADN4612 Design Support Files
  • ADV3200_3201 Design Support Files
  • ADV3202_3203 Design Support Files
  • ADV3224_3225 Design Support Files
  • ADV3226_ADV3227 Design Support Files
  • ADV3228_3229 Design Support Files
  • Are Latch-up immune parts over-voltage fault protected?
  • Are these parts pin-pin compatible with existing parts?
  • Can I leave the exposed pad floating?
  • Can other channels really continue to operate as normal when another channel is in fault?
  • Can the ADG333 be powered from a single 24V supply?
  • Can the ADG452 be powered from a single 24V supply and 3.3V digital supply?
  • Can you explain Power-Off protection and its benefits?
  • Charge Injection
  • confusing redundant temperature spec info in datasheet
  • Cross talk when using ADG490 to mux thermocoules
  • Datasheet for SW01,SW02,SW03,SW04
  • Do you specify switch Off Resistance?
  • EVAL-ADG2128EBZ: What type of cable can I use to connect the board to my signal generator?
  • FAQ: ADG52xxF
  • FAQ: ADG5401F
  • FAQ: ADG54xx
  • FAQ: ADG54xxF
  • FAQ: Digital Crosspoint Switch Frequently Asked Questions
  • FIT reliablity data
  • General Switch/Mux FAQ
  • How do CMOS switch logic control voltage levels affect Idd?
  • How do the fault diagnostics work?
  • How should I manage unused or Not Connected pins?
  • I like the robustness of these parts to PSS issues and the good ESD performance but my application needs lower capacitance and good leakage performance.
  • Is it okay to connect the ADG1611BRUZ's and ADG1436YCPZ's Exposed Pad to Gnd?
  • Latch-up and how are these parts immune to it?
  • MAX14763ETA+ alternative
  • Maximum Pass Voltage on the ADG324x bus switches
  • MEMS Switch Technology FAQ's
  • Multiplexer Settling Time
  • Multiplexor and switch noise specifications
  • Power Supply sequencing requirements for ADG451, ADG452, ADG453
  • Radiation hardened/Space qualified parts
  • Replacement for ADG201ATQ
  • SPICE model not working with Altium Designer
  • Stencil opening for AD8158ACPZ
  • SW06: State of the switch when unpowered
  • Switch & Multiplexer Leakage Measurement Reduction Tutorial
  • Switches and Multiplexers Break-Before-Make Timing Considerations
  • Switches and Multiplexes Support Community
  • The ADG5248F offers �55V over-voltage protection.  What are the keys things I need to      understand about this Over-voltage protected switch compared to using a standard switch in      my application
  • These parts are good, but I need lower on resistance at �15V. Do you have any compatible parts?
  • Theta JA(Junction to Ambient Temperature) and Theta JC (Junction to case Temperature)
  • What are suitable applications for these parts?
  • What are the key benefits of these fault protected switches?
  • What are the system benefits of fault diagnostics?
  • What are the system benefits of overvoltage fault protection with secondary supplies?
  • What happens to the output during an over-voltage event?
  • What if I need to protect my device or downstream circuits against over-voltages?
  • What is the ESD rating of these devices and what is the benefit of the rating?
  • What is the minimum voltage that can be used with these parts?
  • What is the recommended supply sequence?
  • What is the role of the Control Echo Enable bit?
  • What will be the recovery time when switching from a channel in fault to a channel not in      fault?

ADG506: Overvoltage on the input

Q 

Problem with given configuration :

During above operating mode, the multiplexer input (protection circuit)
limits the input voltage to » 720mV. The current drawn by the input during
this phase is » 0.27mA.
This operating condition lasts for 300mS. At the end of this period the
supply to the MUX gets established and the input voltage rises to correct
value.

Question  : 

If a current of 0.27mA flows into multiplexer input for 300mS before its
supply voltage gets established, what effect will it have on the multiplexer
in terms of :

(a) Any permanent damage to the device?

(b) If there is no permanent damage then how many time can you repeat above
operation?

(c) Would you be able to guarantee that the multiplexer can be operated with
above abnormal condition without degradation problem to above mentioned
channel, other channels?

(d) Does above operating condition causes reliability problem?

 

A 

Let me start with a few general notes on semiconductor overvoltage (the state
where the voltage at any IO pin exceeds the supply voltage) and the related
issue of ESD protection.

Any semiconductor IC has basic ESD protection diodes which protect the device
from possible ESD hits due to handling and production. The absolute maximum
ratings must be respected at all times including power up and it is the
designer's responsibility to provide external protection circuitry if the input
is likely to exceed the supplies at any time. The ESD protection diodes serve
two purposes, they protect against static discharge during handling and PCB
manufacture and in addition they provide a limited amount of overvoltage
protection to the device.

These ESD diodes can protect the IC from ESD hits up to about 1.5kV and will
act to clamp the voltage at any pin to within approx 0.3V of the supplies. (So
that's the problem solved right? No not quite.) ESD protection diodes can carry
quite high currents but only for a short period of time so they can protect the
IC from large pulses of short duration (the total energy is still quite low).
The maximum DC current which these protection diodes can carry is approx 5mA.
Therefore unless you can guarantee that the current into in pin will me less
then 5mA you need some kind of external protection. External protection could
be as simple as a series resistor to limit the current into a pin. For example
if the maximum overvoltage voltage applied to a pin will be 5V you need to add
a 500Ohm series resistor in each digital line to limit the current to <5mA. 
The higher you can make this series resistance the better.

A high series resistance in a digital IO line can cause other problems such as
slowing the rise and fall time of high speed digital signals. If connections 
will be accessible by the user, you'll also need to consider ESD protection to
much higher levels than +-1.5kV. You might also want to protect against higher
overvoltages but you don't want to add any more series resistance, so what can
you do? Well, you can do this by adding external Schottky diodes between each
digital IO line and the supply lines. A schottky diode will clamp applied
voltages to within ~0.5V of the supply so the majority of the current will be
diverted via the external diodes (which can carry higher current) and not
through the internal ESD protection diodes. There are other protection
techniques which include use of spark gaps, large capacitors to earth ground,
small choke inductors and more. One the best structures I have seen for
protecting against both overvoltage and ESD is a small series resistor followed
by Schottky diodes to the supplies followed by another small series resistor.

You can see that designing suitable protection circuitry is not a trivial
matter. You need to decide how much protection you need, how much abuse you
expect the card to be subjected to, how much board space and component cost you
can allow, and what test levels you need to meet. Check app notes AN202 and
AN397 for more info.

Now referring to your own specific requirements. To properly analyse, I would
really need to see the circuit schematic prior to the ADG506 and also know the
magnitude of the input voltage.

(a) Any permanent damage to the device?
If you say that under the fault condition that the input is clamped to >720mV
then the ESD protection diodes have started to switch on and are acting to
clamp the input. A current into the pin of 270microamps will not permanently
damage the part. When the ESD protection diode is forward biased, there is
effectively a short from the input pin to the supply, I therefore assume that
you have some circuitry prior to the MUX which is limiting the current. If you
can guarantee that the turn on conditions will not change from the those you
describe then the part will not be damaged.

(b) If there is no permanent damage then how many time can you repeat above
operation?
there will be no permanent damage to the device and there will be no cumulative
damage.

(c) Would you be able to guarantee that the multiplexer can be operated with
above abnormal condition without degradation problem to above mentioned
channel, other channels?
Provided the part is operated within the absolute maximum ratings at all times,
we can guarantee that the part will not suffer damage. However a proper
analysis of the input circuitry would be prudent to look for any other
possibilities due to ESD, incorrect power sequencing, exceeding the power
supply maximum ratings etc. It is preferable that the input protection
circuitry is deliberately designed into the system, rather than simply measure
the voltage and current in one system and presume that all other systems will
operate the same way.

(d) Does above operating condition causes reliability problem?
Again, provided the absolute maximum ratings are always respected, the
condition you describe will not adversely affect the long term reliability of
the part.

If you cannot guarantee the current into MUX is limited under all conditions,
then you may consider using a fault protected MUX such as the ADG508F, not we
only have 8 channel fault protected muxes available therefore two ICs would be
required to replace the ADG506A.
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