The daisy chaining feature of the ADSG1412 enables increased System Channel Density. The SPI interface also has benefits in systems with isolation barriers as it reduces the number of digital lines that cross the isolation barrier. The ADGS1412 also allows robust board communication. It has CRC error detection on its SPI interface. The CRC error detection, along with the other SPI interface error detection features, ensures a robust digital interface.
Yes, you can. The same SCLK, data in and data out lines can be shared with just an additional chip select needed for the ADGS1412.
When multiple ADGS1412 devices are placed in a daisy chain formation the number of digital lines needed to control a large amount of switches is massively reduced compared to using parallel controlled switches. It also eliminates the need for additional serial to parallel converters that are often required when using a great deal of parallel controlled switch. This reduction of logic lines and external component can reduce board by somewhere in the region of 30% in systems with a high channel count.
In Daisy Chain mode all devices share the same and SCLK line, with the SDO of one device forming a connection to the SDI of the next device, creating a shift register. The ADGS1412 enters daisy-chain mode by sending the 16-bit SPI command, 0x2500. When the ADGS1412 receives this command, the SDO of the device sends out the same command as the alignment bits at SDO are 0x25, which allows all connected devices to enter daisy-chain mode in a single SPI frame. A hardware reset is required to exit daisy-chain mode.
When using the ADGS1412 in a write only configuration SCLK frequency of up to 50 MHz can be used. However when read back is required from the device the max SCLK frequency becomes 25 MHz. Please refer to timing diagram in the datasheet for more detail.
The ADGS1412 can be reset by performing either a software reset or a hardware reset. A software reset is done by writing the following two sixteen bit commands consecutively, 0x0BA3 and 0x0B05. A hardware reset is performed by pulling the /VL low.
The digital section of the ADGS1412 goes through an initialization phase during VL power up. This initialization also occurs after a hardware or software reset. After VL power-up or a reset, ensure a minimum of 120 µs from the time of power-up or reset before any SPI command is issued. Ensure that VL does not drop out during the 120 µs initialization phase, as it may result in incorrect operation of the ADGS1412.
The default SPI mode for the ADGS1412 is addressable mode. After power up/reset all switches are open, invalid read/write and SCLK count are enabled and CRC error detection is disabled.
The SPI interface has robust error detection features such as CRC error detection, invalid read/write address detection, and SCLK count error detection. Each error detection feature can be enabled/disabled by using the error configuration register. The error flags register is used to determine if any errors have occurred during SPI communication.
The ADGS1412 is compatible with industry standard SPI modes 0 and 3.
The EVAL-ADGS1412SDZ evaluation board is orderable from the ADGS1412 product page. The EVAL-ADGS1412SDZ is used in conjunction with the SDP and ACE evaluation software. This enables quick and easy evaluation of the analogue and digital sections of the ADGS1412. Also there are No-OS software driver available from the product page that allows you to communicate with the device with your own microcontroller.