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Documents When the cache is enabled, should the interrupt vector table be copied to RAM?
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    • Do I need CL capacitors connected to the high frequency crystal pins, HFXIN and HFXOUT?
    • Does either RSTN or SRSTN fully reset the MAX32600?
    • Does the MAX32600 API automatically copy the interrupt vector table to RAM?
    • For the MAX32600, do I need CL capacitors connected to the 32kHz crystal (xtal)?
    • Is there an EV Kit for the WLP version of the MAX32600?
    • Is VDDA an output?
    • On the MAX32600, does a RSTN event cause the SRSTN to pull SRSTN low?
    • The MAX32600 documentation references a 32kHz crystal (xtal). Should that be 32.768kHz?
    • The MAX32600 EV Kit schematic says ball K10 is LOUT, but the IC datasheet says VSS. Which is it?
    • What is the cache implementation on the MAX32600?
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    • What is the maximum I2C SCL clock rate on the MAX32600?
    • What is the maximum UART baud rate on the MAX32600?
    • What should I look for when I proofread my schematic using the MAX32600?
    • When the cache is enabled, should the interrupt vector table be copied to RAM?
    • Why does my MAX32600 program stop running when I connect the JTAG adapter (Olimex)?
    • Why is the MAX32600 staying in reset?
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When the cache is enabled, should the interrupt vector table be copied to RAM?

Yes, the interrupt vector table should always be copied to RAM when using the cache. After copying the interrupt vector table to RAM, the NVIC Vector Table Offset Register (VTOR) should be updated to point to the address of the table in RAM.
Tags: 000099080 MAX32600-W85B+
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