Why does the MAX30100 power cycle when writing to a register?

Bit 0 of the Interrupt Status register (address 00h) is the power ready flag for the MAX30100.  After initially providing a proper VDD voltage, reading bit 0 will reset the flag.  If the voltage on VDD drops below 1.7V and then increases to a proper voltage as specified in the electrical characteristics table, then the power ready flag will be asserted.  Monitoring this flag will let you know if the voltage at VDD has dipped too low for proper operation of the part.  The power ready flag will not be asserted if the voltage on VDD exceeds the recommended or absolute maximum value.  The bypass capacitor from VDD to GND must be as close to the MAX30100 as possible. The bypass capacitor acts as a local energy storage element and helps keep the VDD supply stable - this is true only if the capacitor is placed as close to the MAX30100 as possible.

In order to avoid issues with VDD dropping to low or going above spec, you should be isolating VDD from the power supply pins of the LEDs.  If this is not done, current spikes from the LEDs may introduce instability to the internal digital circuitry.