FAQ: How to achieve the level translation in ADG324x switches?
Answer:
The signal applied to either the A or B pins of the ADG324x family of bus switches is clamped at the maximum pass voltage level specified in the datasheet. The maximum pass voltage is controlled by parameters, the power supply voltage of the devices, and the logic level applied to the /BE and /SEL pins, allowing the devices to perform the following logic level translation operations using the truth table below:
|
Power Supply Voltage (V) |
/BE Logic Level |
/SEL Pin Logic Level |
Level Translation |
|
3.3 V |
Low |
Low |
3.3 V to 1.8 V |
|
3.3 V |
Low |
High |
3.3 V to 2.5 V |
|
2.5 V |
Low |
High |
2.5 V to 1.8 V |
|
3.3 V/2.5 V |
High |
Don’t Care (X) |
Disconnected |
