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How to detect an open mux channel?

OK, maybe my question and problem are naive but i need to ask anyways....

I have an application using two 32:1 ADG726 analog muxes. The whole purpose is to compute the unknown resistance load on mux inputs by simply injecting a known current and measuring the voltage (after appropriate gain scaling) to compute the resistance on my inputs.The unknown resistance values could vary from 1 ohm to 10,000 ohms. I use the two ADG726 muxes in a differential arrangement to measure the many known loads(up to 32) at the mux inputs.

As long as all unknown loads are connected to the muxes, i have no issues. The problem is that i need to detect when a load is open or absent on any channel w/o affecting the reading accuracy on the rest of the loaded channels. I notice that if I have a load on channel 1 and none for the rest (2 - 32), I get bogus readings for the these unconnected channels(due to leakage current?) and the customer is very unhappy with this problem. In his mind, if a channel is open, it shouldn't display any bogus voltage at all. Unfortunately, these bogus voltage readings are well within the valid range for normal voltages. He doesn't understand why a bogus resistance value is displayed for an unconnected channel...

How can i get rid of these voltages on unconnected channels. I cycle through each mux channel every 80 uSecs. I know unused inputs are supposed to be tied to ground or Vdd but i don't have that option.

Again each channel will have a valid load on it but i need to detect when that load is disconnected due to a blowup or simply when the customer needs to use less than 32 resistive loads for a particular run. The number iof loads varies on a day to day basis. He just doesn't want bogus data to show up on those unused mux channels. Any help would be greatly appreciated.

Thanks,

David

PS

The actual application uses 6 ADG726s for a total of 192 resistive loads to be measured but i limited the above discussion to 32 loads using two muxes for simplicities sake

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  • FEB:

    Thanks for responding to my dilemma. I have included a simplified version of my schematic to show how my board is hooked up. I have a current value i send to each resistor via a DAC and i cycle through the resistors as shown in the schematic and functional diagram via muxes S1,S2 and S3 at an 80usec rate per channel.

    Should one of these resistors break, (and they do!), I would then have an open circuit whose voltage would be undetermined and undesirable giving the user a false sense that we have a valid channel reading. I would like the open-channel condition to either read Vdd (+15V) or Vss (-15V), but not within the some the valid 0 - 5 volt range.

    By the way, we reduce the current as the resistance increases to avoid oversaturating our amps and ADC.

    Thanks,

    David

    MuxTest.pdf
Reply
  • FEB:

    Thanks for responding to my dilemma. I have included a simplified version of my schematic to show how my board is hooked up. I have a current value i send to each resistor via a DAC and i cycle through the resistors as shown in the schematic and functional diagram via muxes S1,S2 and S3 at an 80usec rate per channel.

    Should one of these resistors break, (and they do!), I would then have an open circuit whose voltage would be undetermined and undesirable giving the user a false sense that we have a valid channel reading. I would like the open-channel condition to either read Vdd (+15V) or Vss (-15V), but not within the some the valid 0 - 5 volt range.

    By the way, we reduce the current as the resistance increases to avoid oversaturating our amps and ADC.

    Thanks,

    David

    MuxTest.pdf
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