ADG725/ADG731 programming

Hello GabrielIP,

The /EN bit is used to control the physical switches. When /EN is high, all switches are off, regardless of the settings in the registers.

/CSA and /CSB are used to control the registers. When /CSA or /CSB are high, you can write new A3:A0 values, but they will not change.

Regards,

Sean

     Hello Sean,

Thanks for replying but It does not answer the question.

Please look at table I of the documentation (ADG725 truth table): the first line claims that nothing changes if /CSA and /CSB are high regardless of /EN, the second one that all the switches are off if /EN is high regardless of /CSA and /CSB. This is contradictory: it must be either one or the other.

The question is: what happens if all 3 (/EN, /CSA and /CSB) are high (are all switches disabled or is the switch state unaffected)?

By analogy with the parallel interface of ADG726/ADG732, I suspect that the /EN bit is only taken into account whenever /CSA or /CSB (the corresponding half) is low and that the second line of tables I and II should have 0 in the /CS* columns.

Hello GabrielIP,

If all 3 (/EN, /CSA and /CSB) are high, all switches are turned off and the switch registers are not changed.

Example:

Input1  = [ A3| A2 | A1 | A0 | /EN | /CSA | /CSB] = [0|1|0|0|0|0|0] = S5A – DA, S5B – DB

Output1 = S5A – DA, S5B – DB

Input2 = [0|0|1|0|1|1|1] = S3A – DA, S3B – DB, and "All switches off" and "Retain Previous Switch condition" for both A and B

Output2 = None, All switches off

Input3 = [1|0|0|0|0|1|1] = S9A – DA, S9B – DB, and "Retain Previous Switch condition" for both A and B

Output3 = S5A – DA, S5B – DB

Input4 = [1|0|0|0|0|0|1] = S9A – DA, S9B – DB, and "Retain Previous Switch condition" for B

Output4 = S9A – DA, S5B – DB

In the above example, all the switches are off when /EN is high. The required state of the switch can only be written to if the /CSA and /CSB bits are low. The switch registers were written to twice with different conditions with Input2 and 3, but they retained their condition from Input1. The B output did not change with any input other than Input1.

Regards,

Sean

Hi Sean,

Thanks, this clears up my doubts.

If I understand correctly, this means that I can't disable the A side while having the B side still on. I don't need this capability for the current project, but I need A side and B side to be independently selectable.

This seems to be subtly different from the parallel interface equivalent (ADG726) behavior, which I can't use easily (running out of FPGA I/O pins with 5 chips to program).

Hello GabrielP

It is not possible to individually disable the A and B sections. It is possible to individually select switches, though it has to be done with two writes; see the example above, input3 and input4.

Regards,

Sean

I agree with Gabriel P,

Documentation should be :

A3 A2 A1 A0 EN CSA CSB Switch Condition
 X  X  X  X  0   1   1 Retains Previous Switch Condition
 X  X  X  X  1   X   X All Switches OFF

instead of

A3 A2 A1 A0 EN CSA CSB Switch Condition
 X  X  X  X  X   1   1 Retains Previous Switch Condition
 X  X  X  X  1   X   X All Switches OFF

If EN is '1', it takes priority over CS, so CS features are only available when EN is 0. Which is well explained in Sean example.

Regards