ADG726/ADG732 Programming

Regarding the /EN pin:

Is it internally registred/latched by /WR as shown in Figure 1
OR is it a level sensitive signal, and is active irrespective of /WR and /CS.


I have multiple ADG732 in my project all connected by a common /EN signal and I am unable to switch off one IC
seperately.

Shruthi

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  • There is no typo.

    I am assuming from the datasheet that /EN is latched like A0,A1,A2,A3.

    /EN of first chip goes to /A4 (A4 inverted) and /EN of second goes to A4.

    Since /CS of both are connected to a decoder which goes low only for address 0 - 63,

    (for addresses >63, decoder will not allow the chips to be written to), other addresses

    will not affect the two ADG chips.

    You are suggesting that /EN is not latched with /WR as are A0,A1,A2,A3 ,

    This can easily be confirmed: after latching an address with /WR, keep /WR high

    and by toggling /EN see if selected switch goes on/off or remains always on.

    If /EN is not latched like you are suggesting, then you have to use an external latch for each \EN

Reply
  • There is no typo.

    I am assuming from the datasheet that /EN is latched like A0,A1,A2,A3.

    /EN of first chip goes to /A4 (A4 inverted) and /EN of second goes to A4.

    Since /CS of both are connected to a decoder which goes low only for address 0 - 63,

    (for addresses >63, decoder will not allow the chips to be written to), other addresses

    will not affect the two ADG chips.

    You are suggesting that /EN is not latched with /WR as are A0,A1,A2,A3 ,

    This can easily be confirmed: after latching an address with /WR, keep /WR high

    and by toggling /EN see if selected switch goes on/off or remains always on.

    If /EN is not latched like you are suggesting, then you have to use an external latch for each \EN

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