ADG726/ADG732 Programming

Regarding the /EN pin:

Is it internally registred/latched by /WR as shown in Figure 1
OR is it a level sensitive signal, and is active irrespective of /WR and /CS.


I have multiple ADG732 in my project all connected by a common /EN signal and I am unable to switch off one IC
seperately.

Shruthi

  • A0,A1,A2,A3 and /EN are connected to transparent latches, so when /WR is low,

    these latches continuously respond to changing inputs, and the latches are "latched"

    on the rising edge of /WR.

    If the multiple ADG732 are to be switched off independently, then the /EN of each chip must

    also be activated/deactivated separately.

    Kumar Talreja

  • Working on my PCB /EN does not seem to be latchable like A1,A2...

    Do I need to run seperate /EN lines for each chip (apart from separate /CS)? If so then the chip has a lousy design and the documentation is misleading and needs to be revised.

  • The purpose of /CS is to address one of the ADG732 chips, in a multiple ADG732 design

    where A0,A1,A2,A3 are shared and connected to an address bus, while each /CS goes

    to an address decoder.

    The purpose of /EN is to switch off  all switches(D goes tri-state) when required.

    For example, in a 2 chip design, you connect A0,A1,A2,A3 as shared lines to address bus A0,A1,A2,A3,

    /EN of first chip goes to /A4 of address bus, /EN of second chip goes to A4 of address bus, so this way you have a

    64 channel multiplexer(in this design, only one chip is enabled at a time and the D outputs of both

    are shorted). The processor has to do a write to address values 0 to 63 to select on of the switches.

    (Assuming that /CS of both are shorted and connected to a decoder whose output goes low only for

    address values 0 - 63).

    Kumar Talreja

  • Is there any typo in this advise:

     

    "For example, in a 2 chip design, you connect A0,A1,A2,A3 as shared lines to

    address bus A0,A1,A2,A3,

    /EN of first chip goes to /A4 of address bus, /EN of second chip goes to A4

    of address bus, so this way you have a

    64 channel multiplexer(in this design, only one chip is enabled at a time

    and the D outputs of both

    are shorted)."

     

     

    Let me assume /EN of the first chip goes to A4 and /EN of second chip goes

    to A5.

     

    1.    So that means separate /EN must be connected for each chip.

    2.    Since A4 and A5 will be connected to other chips too, and when A4 and

    A5 are high or low intending to address other chips the ADG726 will

    inadvertently be getting enabled/disabled. Hence it is not a good idea to

    connect Address lines to /EN

     

    So it finally goes down to inferring that dedicated /EN must be connected to

    each chip. Correct?

     

    In my project I am doing a 128:1 multiplixer and I have already jumpered

    separate /EN lines. I wish correction of the errata in the datasheet will

    help future designers. A revision of the Chip itself (with /EN being latched

    like the address lines) would mean a quality product.

  • There is no typo.

    I am assuming from the datasheet that /EN is latched like A0,A1,A2,A3.

    /EN of first chip goes to /A4 (A4 inverted) and /EN of second goes to A4.

    Since /CS of both are connected to a decoder which goes low only for address 0 - 63,

    (for addresses >63, decoder will not allow the chips to be written to), other addresses

    will not affect the two ADG chips.

    You are suggesting that /EN is not latched with /WR as are A0,A1,A2,A3 ,

    This can easily be confirmed: after latching an address with /WR, keep /WR high

    and by toggling /EN see if selected switch goes on/off or remains always on.

    If /EN is not latched like you are suggesting, then you have to use an external latch for each \EN