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If ADN4612 can both support 1.25G 2.5G and 10G ?

My boards use SFP and SFP + interfaces, wanted to support both 1G 2G 10G rate, if this can be support? what required for pcb layout,if have  schematic for reference。

when the rate is 2.5G it need ADN2812 CDR chip,and when the rate is 10G the CDR need bypass.Usually the CDR is at rx side,but needs to be compatible 10G,i used follow way. when the rate is 10G ,the signal flow is R1--T1,when the rate is 2.5G ,the signal flow is R1--T7--CDR--R7--T1.If this design is OK? The signal through ADN4612 will add jitter ,if this effect is large or small in the 2.5G rate?

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  • Hi Tom,

    My apologies for the delayed response.

    1.) A minimum time delay of 100ns is suitable between VCC and DVCC.

    2.) My apologies but inner schematics are internal IP and cannot be shared with customers. We do provide a simplified output circuit diagram in the datasheet that captures the high-level functionality of the transmitter block (Figure 55, Page 27). The current source connected to the emitters of the differntial driver determines the amplitude level of the signal at the output. The current source determines the current level through the 50-ohm resistors in the collectors of the differential driver. The voltage drop across the internal 50 ohm resistors determines the amplitude level. If you connect a 50-ohm load to the transmitter outputs then the voltage level at the load will be reduced by a factor of 2.   The current source is programmable and is derived from the sum of the six current driver elements in the transmitter FFE architecture (Figure 54, Page 27).

    With regards to the change in output common-mode, it is a DC-level and yes, it is just a difference in the impedance the transmitter sees:

    VOCM = VTTO - dVOCM

    dVOCM (DC-Coupled) = ITTO/2 * 25 ohms

    dVOCM(AC-coupled) = ITTO/2 * 50 ohms

    The DC-coupled case sees the far-end 50-ohm termination load with regards to the DC current. Two 50-ohm resistors in parallel = 25 ohms. Half the DC-current stays on chip, the other half of the DC-current is sourced/sunk to the load.

    The AC-coupled case does not see the far-end 50-ohm termination with regards to the DC current, therefore all of the DC current drops across the internal 50-ohm resistor.

    In the AC-coupled case you will see a bigger drop in the output common-mode level than you would in the DC-coupled case.

    The VOL equations on page 33 are just derived from the formulas in Table 22. The 0.75 vs. 0.5 weight is due to the difference in the change in common-mode level due to AC-coupling vs. DC-coupling. I hope this helps. Please let me know if you have any additional questions.


    Regards,

    Jarrod

Reply
  • Hi Tom,

    My apologies for the delayed response.

    1.) A minimum time delay of 100ns is suitable between VCC and DVCC.

    2.) My apologies but inner schematics are internal IP and cannot be shared with customers. We do provide a simplified output circuit diagram in the datasheet that captures the high-level functionality of the transmitter block (Figure 55, Page 27). The current source connected to the emitters of the differntial driver determines the amplitude level of the signal at the output. The current source determines the current level through the 50-ohm resistors in the collectors of the differential driver. The voltage drop across the internal 50 ohm resistors determines the amplitude level. If you connect a 50-ohm load to the transmitter outputs then the voltage level at the load will be reduced by a factor of 2.   The current source is programmable and is derived from the sum of the six current driver elements in the transmitter FFE architecture (Figure 54, Page 27).

    With regards to the change in output common-mode, it is a DC-level and yes, it is just a difference in the impedance the transmitter sees:

    VOCM = VTTO - dVOCM

    dVOCM (DC-Coupled) = ITTO/2 * 25 ohms

    dVOCM(AC-coupled) = ITTO/2 * 50 ohms

    The DC-coupled case sees the far-end 50-ohm termination load with regards to the DC current. Two 50-ohm resistors in parallel = 25 ohms. Half the DC-current stays on chip, the other half of the DC-current is sourced/sunk to the load.

    The AC-coupled case does not see the far-end 50-ohm termination with regards to the DC current, therefore all of the DC current drops across the internal 50-ohm resistor.

    In the AC-coupled case you will see a bigger drop in the output common-mode level than you would in the DC-coupled case.

    The VOL equations on page 33 are just derived from the formulas in Table 22. The 0.75 vs. 0.5 weight is due to the difference in the change in common-mode level due to AC-coupling vs. DC-coupling. I hope this helps. Please let me know if you have any additional questions.


    Regards,

    Jarrod

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