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If ADN4612 can both support 1.25G 2.5G and 10G ?

My boards use SFP and SFP + interfaces, wanted to support both 1G 2G 10G rate, if this can be support? what required for pcb layout,if have  schematic for reference。

when the rate is 2.5G it need ADN2812 CDR chip,and when the rate is 10G the CDR need bypass.Usually the CDR is at rx side,but needs to be compatible 10G,i used follow way. when the rate is 10G ,the signal flow is R1--T1,when the rate is 2.5G ,the signal flow is R1--T7--CDR--R7--T1.If this design is OK? The signal through ADN4612 will add jitter ,if this effect is large or small in the 2.5G rate?

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  • Hi Jarrod,

    For better understand and optimize the application circuit, I have some additional question.

    1/ The power up cycle, Vcc is risen firstly, then DVcc and Vcc1.8 is risen secondly.

    I think that the rising edge of DVcc must be added a delay time behind the rising edge of Vcc.

    Is it correct? the delay time? 1us, 1ms or other?

    2/ For better understand output structure, I want to get some inner schematic of OPx/ONx pins.

    I means, the Programmable Tail Current circuit, how does it set the output level?

    Just current mirrors array has been configurated by different value, or other way?

    The AC and DC coupled outputs have different Vocm, how they work? Just Itto multiply 25ohm/50ohm?

    Vlse=Vtto-0.75 X Vdpp pe----AC Coupled, in DC Coupled, 0.75 is changed to 0.5, how it works?

    I appreciate it you can give me some idea, Thanks a lot!

    Regards,

    Tom

Reply
  • Hi Jarrod,

    For better understand and optimize the application circuit, I have some additional question.

    1/ The power up cycle, Vcc is risen firstly, then DVcc and Vcc1.8 is risen secondly.

    I think that the rising edge of DVcc must be added a delay time behind the rising edge of Vcc.

    Is it correct? the delay time? 1us, 1ms or other?

    2/ For better understand output structure, I want to get some inner schematic of OPx/ONx pins.

    I means, the Programmable Tail Current circuit, how does it set the output level?

    Just current mirrors array has been configurated by different value, or other way?

    The AC and DC coupled outputs have different Vocm, how they work? Just Itto multiply 25ohm/50ohm?

    Vlse=Vtto-0.75 X Vdpp pe----AC Coupled, in DC Coupled, 0.75 is changed to 0.5, how it works?

    I appreciate it you can give me some idea, Thanks a lot!

    Regards,

    Tom

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