Post Go back to editing

If ADN4612 can both support 1.25G 2.5G and 10G ?

My boards use SFP and SFP + interfaces, wanted to support both 1G 2G 10G rate, if this can be support? what required for pcb layout,if have  schematic for reference。

when the rate is 2.5G it need ADN2812 CDR chip,and when the rate is 10G the CDR need bypass.Usually the CDR is at rx side,but needs to be compatible 10G,i used follow way. when the rate is 10G ,the signal flow is R1--T1,when the rate is 2.5G ,the signal flow is R1--T7--CDR--R7--T1.If this design is OK? The signal through ADN4612 will add jitter ,if this effect is large or small in the 2.5G rate?

Parents
  • Hi Tom,

    To truly understand the impact a via's will have on the signal,you really need to model the transmission line path including the via's with either a 2-D or 3-D field solver. Without performing this analysis, it is very hard to determine how much loss the via will cause the signal. Understandably, these tools are not always accessible.

    In General:

    A via will represent a change in the impedance of the transmission line. The impedance change or "discontinuity", which will cause reflections or degradation of the signal, therefore distorting the signal. The geometry of the via (length, diameter, etc.) will either create an inductive or capacitive discontinuity which will determine the magnitude of the increase or decrease in the impedance change. The length of the via will also determine the propagation delay of the signal through the via. If the signal rise time is significantly longer than the via delay (or the via is short in length) then the impact of the signal distortion will most likely be negligible. However, if the delay approaches the rise time of the signal then the impact of the via on the signal will be significant. Therefore, as the data rate increases the signal rise times get shorter approaching the via delay, impacting the signal quality.

    A via stub is the unused portion of the via that is not used to transition the signal from one layer to the next.  It will look like an un-terminated transmission line, which will have a major impact on the signal.  The longer the stub the more significant the signal loss. To reduce or eliminate the via stub we recommend using blind/buried or back-drilled via's, as explained in the ADN4612 datasheet.

    The combination of the signal loss due to a via stub, combined with the attenuation loss of the 10" transmission line trace may make the signal unrecoverable.

    In almost all high-speed serial applications, the use of via's is un-avoidable. When using via's in the transmission line, it is recommended that you eliminate any via stubs. Therefore, it is desirable to either use the full length of the via to transition the signal from the top layer to the bottom layer (i,e, stripline transmission lines). If this is not possible and internal signal layers are required then via stub's will exist. It is generally recommended that you reduce or eliminate the via stub using back-drilling or if this is not an option, it is essential that you keep the via stub as short as possible.

    The recommended power-down cycle of the ADN4612 is the reverse sequence of the power-up cycle.

    VTTx (VTTI and VTTO) -> DVCC and VCC18 -> VCC.

    Regards,

    Jarrod

Reply
  • Hi Tom,

    To truly understand the impact a via's will have on the signal,you really need to model the transmission line path including the via's with either a 2-D or 3-D field solver. Without performing this analysis, it is very hard to determine how much loss the via will cause the signal. Understandably, these tools are not always accessible.

    In General:

    A via will represent a change in the impedance of the transmission line. The impedance change or "discontinuity", which will cause reflections or degradation of the signal, therefore distorting the signal. The geometry of the via (length, diameter, etc.) will either create an inductive or capacitive discontinuity which will determine the magnitude of the increase or decrease in the impedance change. The length of the via will also determine the propagation delay of the signal through the via. If the signal rise time is significantly longer than the via delay (or the via is short in length) then the impact of the signal distortion will most likely be negligible. However, if the delay approaches the rise time of the signal then the impact of the via on the signal will be significant. Therefore, as the data rate increases the signal rise times get shorter approaching the via delay, impacting the signal quality.

    A via stub is the unused portion of the via that is not used to transition the signal from one layer to the next.  It will look like an un-terminated transmission line, which will have a major impact on the signal.  The longer the stub the more significant the signal loss. To reduce or eliminate the via stub we recommend using blind/buried or back-drilled via's, as explained in the ADN4612 datasheet.

    The combination of the signal loss due to a via stub, combined with the attenuation loss of the 10" transmission line trace may make the signal unrecoverable.

    In almost all high-speed serial applications, the use of via's is un-avoidable. When using via's in the transmission line, it is recommended that you eliminate any via stubs. Therefore, it is desirable to either use the full length of the via to transition the signal from the top layer to the bottom layer (i,e, stripline transmission lines). If this is not possible and internal signal layers are required then via stub's will exist. It is generally recommended that you reduce or eliminate the via stub using back-drilling or if this is not an option, it is essential that you keep the via stub as short as possible.

    The recommended power-down cycle of the ADN4612 is the reverse sequence of the power-up cycle.

    VTTx (VTTI and VTTO) -> DVCC and VCC18 -> VCC.

    Regards,

    Jarrod

Children
No Data