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If ADN4612 can both support 1.25G 2.5G and 10G ?

My boards use SFP and SFP + interfaces, wanted to support both 1G 2G 10G rate, if this can be support? what required for pcb layout,if have  schematic for reference。

when the rate is 2.5G it need ADN2812 CDR chip,and when the rate is 10G the CDR need bypass.Usually the CDR is at rx side,but needs to be compatible 10G,i used follow way. when the rate is 10G ,the signal flow is R1--T1,when the rate is 2.5G ,the signal flow is R1--T7--CDR--R7--T1.If this design is OK? The signal through ADN4612 will add jitter ,if this effect is large or small in the 2.5G rate?

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  • Hi Dave,

    I want to know how about the through via can effect the signal integrity, if it has two through vias in less than 10 inch transmission line. Because the ADN4612 spec just said that Blind or Buried via can be used.

    How about the power off time sequence works? If I do not mention the power off time sequence, what will be happened?

    Thanks for your support!

    Yours Sincerely,

    Tom

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  • Hi Dave,

    I want to know how about the through via can effect the signal integrity, if it has two through vias in less than 10 inch transmission line. Because the ADN4612 spec just said that Blind or Buried via can be used.

    How about the power off time sequence works? If I do not mention the power off time sequence, what will be happened?

    Thanks for your support!

    Yours Sincerely,

    Tom

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