If ADN4612 can both support 1.25G 2.5G and 10G ？

Hi Fangquan,

The ADN4612 is an asynchronous, protocol agnostic crosspoint switch, which means it can support any protocol (assuming NRZ modulated) and any data rate up to the maximum rating of 11.3Gbps.  1.25G, 2.5G 10.3G and many more are supported.  You can see from Figure 30 in the datashee that the residual jitter of the ADN4612 is fairly flat across the full range of supported data rates.

Just curious.  Why does your application only require CDR at lower datarates (1.25G or 2.5G), but not at 10Gbps?

You may also be interested in our new ADN2915, any rate continuous tuning CDR, that supports data rates from 0.006Gbps up to 11.3Gbps.

I can send evaluation board schematics off-line.

Dave

hi dave,

      Thanks for you answer ,you suggest ADN2915 is good. But in some low-priced versions ,i need remove CDR module. If you have good idea?

Can you send evaluation board schematics  to me?

Sender: daverowe

Send Time: 2013-08-31 02:16

Receiver: quan fang

Subject: New message: "If ADN4612 can both support 1.25G 2.5G and 10G ？"

EngineerZone

Re: If ADN4612 can both support 1.25G 2.5G and 10G ？

created by daverowe in Switches/Multiplexers - View the full discussion

Hi Fangquan,

The ADN4612 is an asynchronous, protocol agnostic crosspoint switch, which means it can support any protocol (assuming NRZ modulated) and any data rate up to the maximum rating of 11.3Gbps.  1.25G, 2.5G 10.3G and many more are supported.  You can see from Figure 30 in the datashee that the residual jitter of the ADN4612 is fairly flat across the full range of supported data rates.

Just curious.  Why does your application only require CDR at lower datarates (1.25G or 2.5G), but not at 10Gbps?

You may also be interested in our new ADN2915, any rate continuous tuning CDR, that supports data rates from 0.006Gbps up to 11.3Gbps.

I can send evaluation board schematics off-line.

Dave

Sorry for the delay.  Evaluation board materials have been sent offline.

We recommend the ADN2817  or ADN2818 as "recommended/preferred" instead of ADN2812.  ADN2817/8 are newer products.

Hi Dave,

I want to know how about the through via can effect the signal integrity, if it has two through vias in less than 10 inch transmission line. Because the ADN4612 spec just said that Blind or Buried via can be used.

How about the power off time sequence works? If I do not mention the power off time sequence, what will be happened?

Thanks for your support!

Yours Sincerely,

Tom

Hi Tom,

To truly understand the impact a via's will have on the signal,you really need to model the transmission line path including the via's with either a 2-D or 3-D field solver. Without performing this analysis, it is very hard to determine how much loss the via will cause the signal. Understandably, these tools are not always accessible.

In General:

A via will represent a change in the impedance of the transmission line. The impedance change or "discontinuity", which will cause reflections or degradation of the signal, therefore distorting the signal. The geometry of the via (length, diameter, etc.) will either create an inductive or capacitive discontinuity which will determine the magnitude of the increase or decrease in the impedance change. The length of the via will also determine the propagation delay of the signal through the via. If the signal rise time is significantly longer than the via delay (or the via is short in length) then the impact of the signal distortion will most likely be negligible. However, if the delay approaches the rise time of the signal then the impact of the via on the signal will be significant. Therefore, as the data rate increases the signal rise times get shorter approaching the via delay, impacting the signal quality.

A via stub is the unused portion of the via that is not used to transition the signal from one layer to the next.  It will look like an un-terminated transmission line, which will have a major impact on the signal.  The longer the stub the more significant the signal loss. To reduce or eliminate the via stub we recommend using blind/buried or back-drilled via's, as explained in the ADN4612 datasheet.

The combination of the signal loss due to a via stub, combined with the attenuation loss of the 10" transmission line trace may make the signal unrecoverable.

In almost all high-speed serial applications, the use of via's is un-avoidable. When using via's in the transmission line, it is recommended that you eliminate any via stubs. Therefore, it is desirable to either use the full length of the via to transition the signal from the top layer to the bottom layer (i,e, stripline transmission lines). If this is not possible and internal signal layers are required then via stub's will exist. It is generally recommended that you reduce or eliminate the via stub using back-drilling or if this is not an option, it is essential that you keep the via stub as short as possible.

The recommended power-down cycle of the ADN4612 is the reverse sequence of the power-up cycle.

VTTx (VTTI and VTTO) -> DVCC and VCC18 -> VCC.

Regards,

Jarrod

Hi Jarrod,

Thanks for your suggestion! It is very useful.

Regards,

Tom

Hi Jarrod,

For better understand and optimize the application circuit, I have some additional question.

1/ The power up cycle, Vcc is risen firstly, then DVcc and Vcc1.8 is risen secondly.

I think that the rising edge of DVcc must be added a delay time behind the rising edge of Vcc.

Is it correct? the delay time? 1us, 1ms or other?

2/ For better understand output structure, I want to get some inner schematic of OPx/ONx pins.

I means, the Programmable Tail Current circuit, how does it set the output level?

Just current mirrors array has been configurated by different value, or other way?

The AC and DC coupled outputs have different Vocm, how they work? Just Itto multiply 25ohm/50ohm?

Vlse=Vtto-0.75 X Vdpp pe----AC Coupled, in DC Coupled, 0.75 is changed to 0.5, how it works?

I appreciate it you can give me some idea, Thanks a lot!

Regards,

Tom

Hi Tom,

My apologies for the delayed response.

1.) A minimum time delay of 100ns is suitable between VCC and DVCC.

2.) My apologies but inner schematics are internal IP and cannot be shared with customers. We do provide a simplified output circuit diagram in the datasheet that captures the high-level functionality of the transmitter block (Figure 55, Page 27). The current source connected to the emitters of the differntial driver determines the amplitude level of the signal at the output. The current source determines the current level through the 50-ohm resistors in the collectors of the differential driver. The voltage drop across the internal 50 ohm resistors determines the amplitude level. If you connect a 50-ohm load to the transmitter outputs then the voltage level at the load will be reduced by a factor of 2.   The current source is programmable and is derived from the sum of the six current driver elements in the transmitter FFE architecture (Figure 54, Page 27).

With regards to the change in output common-mode, it is a DC-level and yes, it is just a difference in the impedance the transmitter sees:

VOCM = VTTO - dVOCM

dVOCM (DC-Coupled) = ITTO/2 * 25 ohms

dVOCM(AC-coupled) = ITTO/2 * 50 ohms

The DC-coupled case sees the far-end 50-ohm termination load with regards to the DC current. Two 50-ohm resistors in parallel = 25 ohms. Half the DC-current stays on chip, the other half of the DC-current is sourced/sunk to the load.

The AC-coupled case does not see the far-end 50-ohm termination with regards to the DC current, therefore all of the DC current drops across the internal 50-ohm resistor.

In the AC-coupled case you will see a bigger drop in the output common-mode level than you would in the DC-coupled case.

The VOL equations on page 33 are just derived from the formulas in Table 22. The 0.75 vs. 0.5 weight is due to the difference in the change in common-mode level due to AC-coupling vs. DC-coupling. I hope this helps. Please let me know if you have any additional questions.

Regards,

Jarrod