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Question about the state of the clock output at HMC855LC5


My customer asks some questions about the state of the clock output at HMC855LC5.

They say that the data flows of their system are synchonized with the clock output of HMC855LC5.

And they are use lots of HMC855LC5s for synchronizing data lines.

They want to synchronize all data flows to same timming synch.

But the problem is seems to be that the the clock output of HMC855LC5 doesn't have the default initial state (high or low.).

About above things, I already receive your answer like below.

"Just got confirmation from design center that the HMC855 output clock will come up in an unknown state independent of the clock input. I am still checking with the product team, if they have any other suggestion"

So my customer asks additional questions like below.

Would you confirm below questions and let me know your opinions?

Q1) Would you let me know your suggestions about fixing the initial state of HMC855LC5 clock output?

       (It doesn't matter high or low.)

Q2) Could you supply HMC855 with same initial status of output clock after screening test?

      (If you have any experience aboout this case like screening test, please let me know your any opinions.)

Q3) Would you confirm the initial clock output state of HMC955?

    ( If HMC855 can't be fixed the initial clock output state, they are reviwing the use of HMC955.

    So before using HMC955, they want to know  the initial clock output state of HMC955 for preventing the same issue of HMC855.)

Please advise me.

If you have any questions, please let me know.




PS. For your reference, I attach their system block diagram and test results.