ADG836L latching up, possible static problem?

Hi Valued User,

You mentioned a "the first ADG836L in the chain", how many ADG836L is in "chain" mode?  Is it possible to share your schematic so I may understand the circuit better? Also, I would need the following details to confirm your set-up:

• What is Vdd level? By drawing excessive current, do you mean Idd?
• Is Vdd stable? I'm asking this because if Vdd is not stable and there are times that it is not reaching it's required level, ESD diodes are being forwards biased are causing excessive current as you may say.
• What are the INx levels? How fast do you toggle the INx pin?
• What is you analog input signal at Sx/D? How much current is passing through the switch?
• What is your power-up sequence?

A scope shot would be a great help to trace where the problem is coming from. You may place the probes to Vdd, INx, Sx, and Dx of the ADG836L so we can trace what is happening and when does it drawing excessive current.

Also, may I know how did you realize that it is a latch-up condition?

Best Regards,

May

Hi May,

Vdd is 3.3V.  When we first started noticing the problem, we started powering the circuit through a lab supply.  The circuit nominally draws around 140mA, when we get into the error state the circuit starts drawing an Amp of current.  I determined that it was the ADG836L quite by accident, I burned myself on the chip trying to attach a debug cable.  Once things go bad, Vdd starts to oscillate due to the excessive current draw (ADP124 regulator).  

The INx pins are connected to gpio pins of an arm cortex-m0 based microcontroller with a 3.3V logic high level.  During normal operation the INx pins are not switched at all, they are set once at the beginning of a job and stay there for the duration.   

the Sx pins are essentially connected to the high impedance voltage sense line of an RPM systems MPQ programmer.  D1 and D2 are connected to a pogo pin assembly that contacts powered circuits (3V nominal battery supply).  I am using the ADG836L as a switch that allows my to swap the polarity of my voltage sense pogo pins.  During normal operation very little current is flowing through the ADG836L, something on the order of 0.5uA.  The fault occurs when the pogo pins contact the DUT circuit substrate.  

We've gone through the design with a scope and everything is functioning normally except for the ADG836L.  As I mentioned in my original post if the circuit is completely powered down and then powered back up everything works fine again until the mux locks up again.  

Unfortunately I am not able to provide schematics at this time.     

Hi Valued User,

Can you send a scope shot when "fault" condition occurs with probes to Vdd, INx, Sx, and Dx of the ADG836L so we can trace what is happening in the device?

What is your power-up sequence?

For the line "Vdd starts to oscillate due to the excessive current draw (ADP124 regulator)."

- Is there other components/circuit block where Vdd is connected to besides ADG836L?

What do you mean by DUT? Is it a single device under test? Or is there a mini circuit board were a device under test is in it and then will be connected to the pogo pin where the ADG836L is connected to? Please clarify.

Also, "the Sx pins are essentially connected to the high impedance voltage sense line of an RPM systems MPQ programmer.  D1 and D2 are connected to a pogo pin assembly that contacts powered circuits (3V nominal battery supply)". and at the same time "The fault occurs when the pogo pins contact the DUT circuit substrate."

-Can you please elaborate more?

You mentioned that you can't provide a schematic at this time, may I know when do you think you can provide a schematic? Schematics are essential information when debugging a problem. With schematic on hand, we can analyze the circuit behavior and detect where the problem is coming from. Since the schematic is not yet available, can you at least share a simple block diagram of your test circuit?

Best Regards,

May

Hi May,

Is it possible to continue this discussion via email?  I would also need to have an NDA in place before discussing too many more details or releasing a schematic.  Thanks.

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