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ADG612 Production
The ADG611 / ADG612 / ADG613 are monolithic CMOS devices containing four independently selectable switches. These switches offer ultralow charge injection...
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ADG612 on Analog.com

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ADG612 Spice model error: Ron/Roff greater than 1/Gmin



		

			

									
					    ggjesse23
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jul 27, 2017 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    I downloaded the spice model from the AD website for ADG612. I need to run an ac sweep with the part as part of a larger simulation. I am starting with just a basic simulation of the part to show that it works. When I run the simulation in PSpice, I get the following error: "ERROR(ORPSIM-15159): RON or ROFF greater than 1/GMIN for VSWITCH model X_U1.X1.x1.SMOD2."
    
 
    The same error comes up several times in a row in the simulation window with different SMODs, for example: "ERROR(ORPSIM-15159): RON or ROFF greater than 1/GMIN for VSWITCH model X_U1.X2.X2.SMOD4."
    
 
    I am new to PSpice, so my apologies if I am missing something basic. 
    
 
    Many thanks for any tips. 
    
 
    -JR
    
									
			        
		
    

				
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    Tags: 
                                            
                 Dual-Supply Analog Switches and Multiplexers
                
                                                    
                 Analog Switches Multiplexers
                
                                                    
                 switches and multiplexers
                
                                                    
                 ADG612
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jul 30, 2017 6:43 PM
            
            
					
      
	
      

		
		
      
					
      Hi JR,
      
 
      Switch bandwidth can be can be represented as a low pass RC filter, where: R is the on resistance of the switch and C is Con. Yes, bandwidth is greatly affected by the capacitance at the output pins and also with capacitive load (Cload).
      
 
      If you're testing the bandwidth capability of the ADG612 by the configuring it via 4:1 mux. With this configuration, it would seem like there are four CDoff in parallelI, thus capacitance the the output pin of the channel adds up. I would suggest to simply place external capacitors at the output pin of the channel your testing. This way we can avoid transient errors in the simulation. 
      
 
      Regarding the simulation error, you can try updating the spice model and start from there. You may change the Roff parameter from 1E20 to 1E11 of the vswitches SMOD2, SMOD3, SMOD4, SMOD5, and SMOD6. 
      
 
      
 
      For your design requirement, can you share additional information and maybe I could be of help?
      
 
      Best Regards,
      
 
      May
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jul 30, 2017 6:43 PM
            
            
					
      
	
      

		
		
      
					
      Hi JR,
      
 
      Switch bandwidth can be can be represented as a low pass RC filter, where: R is the on resistance of the switch and C is Con. Yes, bandwidth is greatly affected by the capacitance at the output pins and also with capacitive load (Cload).
      
 
      If you're testing the bandwidth capability of the ADG612 by the configuring it via 4:1 mux. With this configuration, it would seem like there are four CDoff in parallelI, thus capacitance the the output pin of the channel adds up. I would suggest to simply place external capacitors at the output pin of the channel your testing. This way we can avoid transient errors in the simulation. 
      
 
      Regarding the simulation error, you can try updating the spice model and start from there. You may change the Roff parameter from 1E20 to 1E11 of the vswitches SMOD2, SMOD3, SMOD4, SMOD5, and SMOD6. 
      
 
      
 
      For your design requirement, can you share additional information and maybe I could be of help?
      
 
      Best Regards,
      
 
      May
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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