ADG612 Spice model error: Ron/Roff greater than 1/Gmin

Hi JR,

I don't understand why you need to tie up all the Drains (D1 to D4) into a single node. I would think this causes your transient simulation errors.

If switches 2, 3, and 4 will not be used, then you may leave the D2, D3, and D4 pins floating as long as S2, S3, S4 and IN2, IN3, and IN4 are tied up to ground.

Also, may I know the output load of the ADG612? the figure attached doesn't show this information.

Let me know if this helps.

Best Regards,

May

I found an error -- had the negative terminal of the DC supply on the input, should have been positive terminal. Did not affect simulation results. New schematic attached here.

Thanks, 

JR

Hi May,

Thank you for your suggestions.

I would agree that it is not ideal to have the drain nodes connected, but this is actually the reason for the simulation in the first place due to constraints in how the part must fit into a larger design. The goal of the simulation is to see if the bandwidth for the output is large enough to fit the design requirements in spite of the resultant output capacitance from the tied-together drains.

However, I tried your suggestion, disconnecting the drains and tying the irrelevant drains to ground. I also show a representative load here of 1k to ground, just for the purpose of the simulation. See the attached schematic (apologies for the messiness, just hacking it up here). Unfortunately, I get the same errors in the PSpice simulation, this "Ron or Roff greater than 1/Gmin for VSwitch..." error (see above).

Thanks again for your help,

JR

Hi JR,

Switch bandwidth can be can be represented as a low pass RC filter, where: R is the on resistance of the switch and C is Con. Yes, bandwidth is greatly affected by the capacitance at the output pins and also with capacitive load (Cload).

If you're testing the bandwidth capability of the ADG612 by the configuring it via 4:1 mux. With this configuration, it would seem like there are four CDoff in parallelI, thus capacitance the the output pin of the channel adds up. I would suggest to simply place external capacitors at the output pin of the channel your testing. This way we can avoid transient errors in the simulation. 

Regarding the simulation error, you can try updating the spice model and start from there. You may change the Roff parameter from 1E20 to 1E11 of the vswitches SMOD2, SMOD3, SMOD4, SMOD5, and SMOD6. 

For your design requirement, can you share additional information and maybe I could be of help?

Best Regards,

May

This is a pretty old thread for the ADG612 but I am using this device for an application where I do tie all of the D1-D4 lines together for a mux.  From the spice model/cir file on the ADG612 webpage, it indicates the following items are modeled

* Begin Notes:
* The model will work on Vdd/Vss from 0.5V to 5V single supply and +/-0.5V to +/-5V dual supply.
* The model provides parametric specifications at +/-5V only and is not variable with Vdd and Vss changes. Please see datasheet spec table.
*
* Parameters modeled include:
* On Resistance
* Ton and Toff
* Break-Before-Make
* Off Isolation
* Crosstalk
* Supply Currents: Iss/Idd
* Bandwidth
* Charge Injection
* Connections

I would have thought that the above model available would have had all of the parasitic capacitances already factored in given that bandwidth is a modeled item but apparently not.  It seems that the missing element here is just an extra 5pF capacitance load to ground at each Dx connection points?     

dennis