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ADG839: Negative voltage switching

emilzacharia
on Sep 27, 2017

Hi,

I found the following circuit in a reference board where they use ADG839 as a load switch to a negative voltage.

The VIN varies from 0V to -3.3V referenced to GND.

GPIO_IN is a GPIO input from an FPGA which can give HIGH(2.5V) and LOW(0V).

Using the GPIO, they control whether VIN is passed to VOUT or not.

I couldn't understand the circuit eventhough I tried.

Please help me to understand how it works and design a similar circuit in which GPIO_IN is a GPIO input from an FPGA which can give HIGH(1.8V) and LOW(0V).

Also, VIN varies from 0V to -2.4V referenced to GND in my case.

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  • 0
    •  Analog Employees 
    on Sep 29, 2017 2:10 AM

    Hi Emilzacharia,

    From my understanding of the schematic above:

    • It seems that the ADG839 is level shifted to the negative voltage with GND to -3.3V and Vdd to ground (0V). Checking at the ADG839 datasheet, this configuration might be working because the magnitude of Vdd to GND did not exceed the Absolute Maximum Ratings specifications of 4.6V.

    • Considering the voltage divider network R3 and R8, and the GPIO_IN of 2.5V(H) and 0V(L), the digital input to IN can be computed as -1.22V and -2.12V respectively. Problem here is that, with Vdd and GND level shifted, the digital logic thresholds (VIH and VINL) that determines the state of the switches, are not guaranteed anymore. Thus it is not ensured which Source (S1 or S2) is connected to the Drain (D). 

           Please be reminded that we can only guarantee specifications provided by the datasheet within its specified               operating conditions.

    Regarding your application, with 1.8V level from FPGA and VIN varies from 0 to -2.4V, I would recommend two options that you can choose from:

    • First option is to use the ADG1636, as this is operational at +/-3.3V dual supply. So VIN of 0V to -2.4V can be accommodated. However, the digital logic input is not compatible with 1.8V (as VIH = 2.0 V), so you may want to consider adding a level translator here.
    • The second option is to use the ADGS1612 (to be released soon), which is a low voltage (+/-3.3V to +/-8V dual supply operation), low Ron, Quad SPST switch with SPI interface, and is 1.8V logic compatible. This can be configured to an SPDT with BBM operation. The low dual supply operation can cater VIN = 0V to -2.4V and the 1.8V FPGA digital driving levels.

    Let me know if this helps.

    Best Regards,

    May

Reply
  • 0
    •  Analog Employees 
    on Sep 29, 2017 2:10 AM

    Hi Emilzacharia,

    From my understanding of the schematic above:

    • It seems that the ADG839 is level shifted to the negative voltage with GND to -3.3V and Vdd to ground (0V). Checking at the ADG839 datasheet, this configuration might be working because the magnitude of Vdd to GND did not exceed the Absolute Maximum Ratings specifications of 4.6V.

    • Considering the voltage divider network R3 and R8, and the GPIO_IN of 2.5V(H) and 0V(L), the digital input to IN can be computed as -1.22V and -2.12V respectively. Problem here is that, with Vdd and GND level shifted, the digital logic thresholds (VIH and VINL) that determines the state of the switches, are not guaranteed anymore. Thus it is not ensured which Source (S1 or S2) is connected to the Drain (D). 

           Please be reminded that we can only guarantee specifications provided by the datasheet within its specified               operating conditions.

    Regarding your application, with 1.8V level from FPGA and VIN varies from 0 to -2.4V, I would recommend two options that you can choose from:

    • First option is to use the ADG1636, as this is operational at +/-3.3V dual supply. So VIN of 0V to -2.4V can be accommodated. However, the digital logic input is not compatible with 1.8V (as VIH = 2.0 V), so you may want to consider adding a level translator here.
    • The second option is to use the ADGS1612 (to be released soon), which is a low voltage (+/-3.3V to +/-8V dual supply operation), low Ron, Quad SPST switch with SPI interface, and is 1.8V logic compatible. This can be configured to an SPDT with BBM operation. The low dual supply operation can cater VIN = 0V to -2.4V and the 1.8V FPGA digital driving levels.

    Let me know if this helps.

    Best Regards,

    May

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