I found the following circuit in a reference board where they use ADG839 as a load switch to a negative voltage.
The VIN varies from 0V to -3.3V referenced to GND.
GPIO_IN is a GPIO input from an FPGA which can give HIGH(2.5V) and LOW(0V).
Using the GPIO, they control whether VIN is passed to VOUT or not.
I couldn't understand the circuit eventhough I tried.
Please help me to understand how it works and design a similar circuit in which GPIO_IN is a GPIO input from an FPGA which can give HIGH(1.8V) and LOW(0V).
Also, VIN varies from 0V to -2.4V referenced to GND in my case.
From my understanding of the schematic above:
Please be reminded that we can only guarantee specifications provided by the datasheet within its specified operating conditions.
Regarding your application, with 1.8V level from FPGA and VIN varies from 0 to -2.4V, I would recommend two options that you can choose from:
Let me know if this helps.