In the picozed SOM, the clock signal to AD9361 is given via a mux/demux AG771 device. The ADG772 device takes, two inputs, one from 40MHZ crystal oscillator and the other as external clock input. In the schematic of SOM, it is indicated that, the external clock signal must be 1.3Vpp max. But when measured, the 40MHZ crystal oscillator(y4) gives 40 MHz clock signal at 1.8vpp which is going as one input(pin3) of ADG772 and it is a square wavw signal with amplitude level from 0 to 1.8V. If one i/p of mux can be 1.8Vpp, whether I can give the other input(pin1) the same signal which is taken from a TCXO, LVCMOS signal with 1.8vPP signal. Please clarify. I have planned to use a TCXO for the external clock signal generation and a clock buffer with voltage translator to translate the clock from 3.3V to 1.8Vpp clock signal to pin 3 of ADG227. I am not getting 1.3VPP o/p TCXO or clock buffer to feed 1.3VPP clock signal to pin 3of ADG772. Also in the data sheet of ADG772, the o/p voltage levels are not mentioned. In SOM, the power supply for ADG772 is 3.3V. If that is the case, whether ADG772 o/p(pin 2) will be 3.3VPP ?. Please clarify
I notice that this query has been unanswered for some time. is this still an issue for you?
yes. Also the supply voltage to the ADG772 is 3.3V, how 1.3VPP signal to "9361_XTAL" net is ensured
The ADG772 has a CMOS switch architecture which is detailed here in MT-088. https://www.analog.com/media/en/training-seminars/tutorials/MT-088.pdf
This architecture provides a channel for the signal to pass through and does not buffer the signal or level translate it. So if a 3.3V VDD is supplied to the ADG772 it means that the ADG772 will be able to pass signals up to 3.3V.