4Wire Measurment - Influence of Leakage Currents

Hi all,

I have a conceptual question about modeling leakage currents in CMOS analog multiplexers in a 4‑wire RTD measurement setup, and I’d appreciate some expert feedback.

Setup (simplified):

• DMM: Keysight 34465A in 4‑wire RTD mode (Pt1000)
• 4‑wire connections (force+/force−, sense+/sense−) to multiple Pt1000 sensors
• Channel selection via CMOS analog multiplexers (e.g. ADG7xx/ADG79x‑class devices)
• Ideally, all four leads per RTD are switched through a MUX path so that only one sensor at a time is connected to the DMM.

I have read quite a bit about internal leakage mechanisms (reverse‑biased PN junctions, parasitic diodes, “channel on leakage”, “off leakage”, etc.). For example, TI’s application brief models a MUX channel as an ideal switch plus a leakage current source at the channel pin that flows through the input impedance of the following stage and creates a DC offset error TI_MUX_ErrorInformation.pdf. The ADG798/ADG5298 paper similarly uses “channel on leakage” as a key per‑channel parameter 67745-high-prec...nments.pdf.

My problem is not whether leakage exists, but how to model it:

• In theory, one could go down to transistor level (P‑MOS/N‑MOS, body diodes) and derive leakage for each PN junction.
• In practice this is not tractable, and the datasheets already collapse all of that into per‑channel specs like “drain/source/channel leakage”.

So I’d like to model my setup at system level by:

• assuming an effective leakage current Ileak,effI_\text{leak,eff}Ileak,eff​ at the sense node,
• composed of on‑leakage of the active MUX channel plus off‑leakages of all inactive channels that are “visible” at the bus,
• and then using ΔU=Ileak,eff⋅Rin\Delta U = I_\text{leak,eff} \cdot R_\text{in}ΔU=Ileak,eff​⋅Rin​ → ΔR=ΔU/Imeas\Delta R = \Delta U / I_\text{meas}ΔR=ΔU/Imeas​ → $\Delta T=\Delta R/(dR/dT)$ to estimate the RTD temperature error.

My concrete questions:

1. Mapping datasheet → model:
   When a datasheet specifies “drain leakage”, “channel on leakage”, or I_S(off)/I_D(off):
   Is it reasonable to interpret these values as an effective leakage current source at that physical pin (e.g. the COM/sense node), as TI’s model suggests? In other words:
   – active channel → on‑leakage at the COM pin,
   – inactive channels → off‑leakage at their pins that are connected (directly or via COM) to the sense bus?

2. Direction/sign of leakage currents:
   Datasheets usually give magnitudes (±x nA) but not exact directions.
   From your experience, is it acceptable at system level to model symmetrically distributed leakage currents (some pulling current out of the sense node towards the rails, some pushing current into it), such that a realistic net leakage in the pA range results?
   Or are there common assumptions (e.g. “dominantly towards VDD”) that you would apply in such a model?

3. Abstraction level:
   For an uncertainty analysis, is it technically sound to ignore the detailed P‑/N‑MOS junction level and rely on the per‑channel leakage model at the sense node (as TI/ADI effectively do), or am I missing an important effect by not going down to transistor detail?

4. Practical observation:
   Experimentally, I see only about 0.1–0.2 °C difference between measurements “with MUX” and “without MUX” for Pt1000. Back‑calculating this corresponds to an effective leakage current through the DMM input in the few‑pA range.
   This is much smaller than the nA worst‑case figures from the datasheets, but seems plausible if many individual leakages partially cancel.
   Would you agree with this interpretation, or are there more typical explanations for such small net currents?

I want to justify this modeling approach cleanly in a write‑up and I’m looking for best practices on how MUX leakage is usually modeled in 4‑wire measurement chains:
– purely as per‑channel leakage at the sense node,
– or with additional assumptions about current distribution / direction?

Thanks a lot for any insights!