Category: Hardware
Product Number: ADGS1414D
1. How much current does SDI consume when communicating?
2. How much is the internal pull-up resistance of SDO in ADGS1414D?
1. How much current does SDI consume when communicating?
2. How much is the internal pull-up resistance of SDO in ADGS1414D?
Thank you for your answer!
I have a more question
1. If the SDI draws around 1 mA of current, the voltage becomes 3.3 V – 1.25 V = 2.05 V. Should I understand this 2.05 V as the minimum voltage? (Please refer to the table below.)
2. If the above description is correct, in the case of ADGS1414D, when connected by Daisy chain, SDI acts as SDO's source current, so SDO can't come out 3.3V, is it correct?
Hi,
The SDI should never draw 1mA of current, see spec table below.
Here are some scope plots of the ADGS1414D whilst in Daisy Chain mode with SCLK @ 2.5 MHz. Vdd = +15V, Vss = -15V, and Vs = +10V. Temp = 25C.
As you can see SDI of unit one is 3.3V, so is SDO of unit 1 and SDO of unit 2.
SPI Mode 0, VL=3.3V :
SPI Mode 3, VL=3.3V :
Regards,
Karen
This is the result of measuring the SDO waveform of the 3rd ADGS1414D by SPI frequency by connecting 3 ADGS1414D by Daisy chain.
1. 2.5MHZ (As measured by the head office, SDO output is measured at 3.2V.)
2. 5MHZ (The SDO output is at 3.2V, but the waveform at Rising starts to lie down.)
3. 12.5MHZ (The SDO output is 2.68V, and the load current increases as the frequency increases, causing the waveform to lie down more and fail to rise to 3.2V.)
4. 25MHZ (The SDO output is 1.92V, and as the frequency increases, the load current increases further, resulting in a lower voltage output.)
The part where the load current increases for each frequency is shown in Datasheet, so I understand, but the problem is that the waveform is lying down too much compared to the increasing load current.
25 MHz based on Datasheet, 120uAtyp for SDI based on VL = 3.3V.
Currently, we proceed with control with FPGA, and the current allowable current per IO is 16mA.
When three ADGS1414D are connected by Daisy chain, the current capacity of FPGA IO is sufficient even if it is operated at 25 MHz, which is a separate issue from FPGA IO strength, and the load current capacity of 1A is sufficiently being tested for VL voltage.
Can you check the SDO waveform at 25 MHz?
If you get the same result as us, please check what the cause is and if there is a solution,
If there is a 3.3V output, which is a different result, I would like you to comment on which part we should change additionally.
Judging from your scope plots here, it looks like you are having an issue with capacitance, which is something that doesn't appear delay the system at 2.5MHz enough to read the SDO at any lower than 3.2V, but is certainly is adding a slow rise on the rising edge.
I would suggest checking your circuit / board. Are there any parasitic capacitances connected in between your two ADGS1414Ds?
From the datasheet below, t8, t9, t10, and load cap below should be satisfied if SDO will be used.
