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ADN4604: I2C ACK

Category: Hardware
Product Number: ADN4604


I have got a question regarding the I2C read operation. The datasheet of ADN4604 states, that at the end of a read transaction, the master has to send an ACK (low):

With my master (Xilinx UltraScale+ device), I always observe a NACK (high) at the end of such a transaction (reading device ID at 0xFF):

This document from TI also states, that at the end of a I2C read transaction a NACK is expected:

Which behavior is correct?

Thanks for your assistance!

Best regards, ipg

  • Hi ipg,

    Thank you for your interest in ADN4604.

    Both are okay.

    You may follow the FPGA sending NACK at the end of a read transaction to signify that you have received the data you need. Here's ADIs article about I2C Primer: What is I2C? (Part 1) | Analog Devices

    For ADN4604's point-of-view, there is a section in the datasheet showing 4 options (13-a to 13-d) you can choose to do after doing the steps 1 to 12 of I2C Data Read.

    Figure 47 is valid following option 13-a.

    Hope this helps.

    Best regards,

  • Hi Peevee,

    thanks for your answer, but I think, you may not got the question correct. The stop conditions from step 13 are clear for me.

    My question is about step 12. In your datasheet, there is stated, that at the end of the read transfer, an ACK should be send by the  m a s t e r.

    But in your I2C Primer (you mentioned), there is a NACK stated for the last received byte.

    What does ADN4604 expect for the last bit (before STOP), an ACK or a NACK?

    Thanks and best regards,


  • 0
    •  Analog Employees 
    •  Super User 
    in reply to ipg

    Hi ipg,

    Both are okay.

    If you want a definitive answer, if you are done with the read transaction and no longer wants to receive data, send a NACK after the last byte.

    Best regards,