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ADG715 Trise Tfall

Category: Datasheet/Specs
Product Number: ADG715

Hi,

I am checking the ADG715 datasheet and it talks about ton and toff but not about trise or tfall for the signals that go through the SPSTs. I am planning to connect a signal of 50MHz frequency that will be switching with a trise < 2ns and a tfall < 2ns. Since the octal single-pole, single-throw (SPST) switches are complementary metal-oxide semiconductor (CMOS), is known there would be present a specification of trise/tfall and it is important for my application to understand what is the limit.

If this particular component will not fullfill my needs, could you recommend one that could work with this constraints?

Regards

Jose Enrique

Top Replies

    •  Analog Employees 
    Aug 3, 2023 in reply to JoseEnrique +1 verified

    Hi  ,

    Thanks for the clarification.

    We don't have any data about the rise/fall time limitation of the signals passing through the source and drain of the switch as this was not tested in production…

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  • Hi  ,

    Table 5 of the ADG715 datasheet mentions that the SCL and SDA's maximum rise and fall time are around 250-300 ns. This only has a maximum of 400 kHz clock frequency.

    We have ADGS1414D which is an octal switch that is SPI-controlled. This can be used at the clock frequency of 50 MHz. It has a rising and falling edge time of 30 ns maximum.

    Let me know the other system requirements of your application.

    Best regards,
    Christian

  • Hi Christian,

    Thanks for your answer but I am more interested in knowing if there is any limitation in the signal frequency once the  switch is turned on. The I2C bus frequency is ok, but is more about the signal that is going to be carried by the data line enable by the switch. We want to use the switch to enable and disable a clock signal of 50MHz. The question is if there would be any effect on the rise, fall times of the clock between the input and the output once the switch is turned on.

  • Hi  ,

    Thanks for the clarification.

    We don't have any data about the rise/fall time limitation of the signals passing through the source and drain of the switch as this was not tested in production. I tried simulating this setup given the on-resistance and capacitance values in the datasheet. I don't see any problems with the output signal. A small delay in reaching the high and low levels of the clock is expected due to the RC combinations. A reduction in signal amplitude is also expected due to the on-resistance.

    I can try to test it on a bench for a unit or two but, this will take some time. And we can't guarantee that the performance is the same in all the ADG715 units. 

    Best regards,
    Christian

Reply
  • Hi  ,

    Thanks for the clarification.

    We don't have any data about the rise/fall time limitation of the signals passing through the source and drain of the switch as this was not tested in production. I tried simulating this setup given the on-resistance and capacitance values in the datasheet. I don't see any problems with the output signal. A small delay in reaching the high and low levels of the clock is expected due to the RC combinations. A reduction in signal amplitude is also expected due to the on-resistance.

    I can try to test it on a bench for a unit or two but, this will take some time. And we can't guarantee that the performance is the same in all the ADG715 units. 

    Best regards,
    Christian

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