Post Go back to editing

ADGS5412 SPI interface diagram possible error

The Address Mode section on page 22 of the datasheet for the ADGS5412 states that SDO clocks data out on SCLK falling edges.  However, Figure 39 and Figure 40 show SDO clocking data out on the rising edge.

Also, I find it strange that read data starts clocking out on the 9th falling edge instead of the 8th falling edge.  Starting on the 9th falling edge means that a receiver that clocks in data from SDO on rising edges needs to use the 10th through 17th rising edges.  There isn't an 17th rising edge in Address Mode.  Is the 9th falling edge really when read data start?

I appreciate you help understanding the correct alignment for the SDO output.

Parents Reply Children
No Data