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AD5144 Daisy-Chain Questions


I am designing a circuit that wants 4 AD5144 chips to be daisy-chained together. The SPI bus that is interfaced with them is also shared with another chip that will be active when the ~SYNC pin on the digipots are pulled high (chip select disabled). When the ~SYNC pin is pulled high are the SDI and SDO pins pulled into a high impedance state? If they are not then there could be issues with the other chip that will be using the SPI lines during that time. 

I am also curious if there is a maximum allowable number of the AD5144s that can be daisy-chained together? I was not able to find concrete information to answer either of these questions in the datasheet. 

Thank you for the help!

  • Hi

    When /SYNC is pulled high, the SDO is placed in high impedance state. Further, with /SYNC high, SCLK is gated and so any data on SDI is ignored. All that is needed is to meet the timing specifications as given in the datasheet.

    There is no maximum allowable number of AD5144s that can be daisy chained together, as long as SCLK-SDI delay is met for all the devices. For this, you need to slow down the SCLK depending on the number of devices.