ADG2128 holds SDA line Low, I2C timing issue?

We have an I2C bus with quite a few devices attached, including one ADG2128 set to address 0x70. Recently we found a strange occurrence that after certain data "E1" in a stream of data addressed to a different device, ADG2128 would hold the SDA line low. My working hypothesis is ADG2128 somehow interprets this data E1 as a calling it to read, i.e., reading its address 0x70. When ADG2128 holds SDA line low, no other data can be transmitted and I2C host throws an error.

I've tested this hypothesis by holding ADG2128 in reset. Lo and behold, the error no longer occurs.

I've taken an oscilloscope grab of the I2C bus during this error. In this case the data stream is addressed to I2C device at address 0x34.

Here's the complete data transmission up to the point of error:

Zooming in to look at the last byte of data before SDA is held low:

The toggles of SDA and SCL at the cursors is an Ack by device 0x34 to the previous data byte. I am wondering if ADG2128 is mistaking this toggle as a Start condition.

Could it be possible? What ADG2128 I2C timing requirement did this bus transition violate to cause ADG2128 to respond erroneously?

  • Hi Paul,

    We are currently looking into this and get back to you.

    Best regards,
    Christian

  • Hi Paul,

    Thanks for your patience.

    Upon checking the datasheet, the SDA line is pulled LOW when the device address corresponds to the transmitted address during the ninth clock pulse, known as the acknowledge bit. During this stage, all other devices in the bus remain idle.

    In the High-Speed I2C Interface section of the datasheet, the device supports the high-speed (3.4 MHz) I2C interface. And, only the -HS models provide this added performance.
    Have you checked the current model you are using if the high-speed feature is included?

    What device speed are you currently working?

    Also, have you tried a speed lower than 3.4 MHz?
    Best regards,
    Christian

  • Thank you Christian for your reply.

    We are using ADG2128YCPZ and definitely not the -HS version.

    We are running the I2C bus at 400kHz - as can be seen from the scope capture in my initial post, 2 clock cycles per 5us translates to 400kHz - which ADG2128YCPZ should support.

    My question is, whether it is possible for ADG2128YCPZ to interpret the previous Ack bit - zooming in and shown below - as its Start condition, even though it's not expected to do so.

    Please let us know what you think.

    Thanks,

  • Hi,

    Thanks for your patience.

    Based on this zoomed-in scope shot, it is clear that this is an ACK of the previous data since the HIGH-low transition of the SDA line happens when the SCL is LOW. The start condition is when the SCL is HIGH, and the SDA is HIGH-LOW.

    Have you tried disconnecting the ADG2128 and checking the SDA if it will be held high? Or using a different device address? Also, have you tried using another data sequence and checking if the error is still evident?

    Best regards,
    Christian

  • Thank you Christian for your reply. 

    Indeed the zoomed in view was an Ack of a previous data. But somehow ADG2128 responds to 0xE1 after this Ack bit.

    Yes I  removed ADG2128 from our board and the error no longer appeared. 

    I could try a different device address. But until we understand the error mechanism, I'm afraid the error may reappear with a different data pattern.

    Would you be able to reproduce the error in your lab and help us figure out where it went wrong?

    Oh yeah by the way this error does not happen with all our boards, which means not all ADG2128 will show this problem with the timing shown on my scope captures.

    Thanks, 

    Paul